Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm trying to disable shift enable in function mode.
This is the VHDL code: i_scan_shift_enable <= '0' when scan_mode_in = '0' else scan_shift_enable;
So "scan_shift_enable" is driven from a pad and "i_scan_shift_enable" drives the flops.
However I can't seem to keep net i_scan_shift_enable preserved and even if I did would it be a valid pin for the DFT tools to hookup to.
How is this generally done? Is it necessary to instantiate tech cell, preserve and hookup to the output pin?
I have seen tech cells instantiated for this purpuse, but it isn't absolutely necessary.
Using a hierarchical pin for this purpose is quite useful. If you can make i_scan_shift_enable a hierarchical pin, then you can define your shift_enable as follows:
define_dft shift_enable -name SE -hookup_pin [find / -pin <hier_path>/i_scan_shift_enable] -hookup_polarity non_inverted [find / -port scan_shift_enable]
When connecting scan chains, RC will know to connect to the <hier_path>/i_scan_shift_enable pin. But, when writing out interface files for Encounter Test, RC will know that the shift_enable port is scan_shift_enable.
You are correct that you cannot rely on net names to be preserved throughout the flow. But, you can generally rely on hierarchical pins to remain throughout the flow (at least through synthesis), as long as you prevent them from being ungrouped.
In reply to bmiller:
In reply to Terry2000:
Have you checked that SE got connected to the clock gaters cells correctly?
Is there actually a controllable path from the port scan_shift_enable to the clock gater enable cells? If not, that is the reason for the failure. You can check the controllablity of this path by using the dft_trace_back command:
Usage: dft_trace_back [-mode <integer>] [-polarity] [-continue] [-print] <pin|port> [-mode <integer>]: trace back one level under the specified mode (0-3). 0: no constant propagation, 1: tied-constant propagation, 2: tied-constant and test-mode propagation, 3: tied-constant, test-mode and shift-enable propagation [default: 3] [-polarity]: also return whether the polarity changes through the trace [-continue]: continue the trace back until PI, sequential gate, complex instance or constant is reached [-print]: print the status and pin at every trace back <pin|port>: pin or port to start the back-trace from
Use -mode 3 to propagate shift_enable.
You could also try temporarily using a primary input for SE (rather than using -hookup_pin) just to prove to yourself that controlling the clock gaters with SE is ok. But, I believe this to be a better solution than using scan_mode.