What is the default algorithm used for hardware implementation of division operation when synthesised using RC Compiler. Like the code below
quot[n:0] = divd/dvsr;
remi = divd%dvsr;
You want to know the internal behaviour of a commercial product. Cadence will never publish such a thing..Division in Verilog "/" is a fixed-point division, from which RTL Compiler generates division hardware by using synthetic operator DIV_UNS_OP or DIV_TC_OP. There are two other synthetic operators DIV_UNS_IEEE_OP and DIV_TC_IEEE_OP but I have not been able to force RTL Compiler to use them. Below this resolution nothing is visible to the user.
Maybe this can give you a hint..
In reply to Sporadic Crash:
Thanks a lot for your response.
I am just intersted to know what algorithm is used to synthesis the hardware like one among below or some other algorithm which is Cadence proprietary..?
Restoring division, Non-restoring division, SRT division, Newton–Raphson division, Goldschmidt division