Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
when should i use interposer and spacer in sip？
thanks in advance!
Spacers are used to represent the physical spacer objects placed between dies in a die stack. The spacer provides separation between the two die, be it for electrical/thermal/etc. reasons or to ensure there is adequate vertical spacing so that, when the upper die is mounted above the lower die, the lower die's bond wires will not be damaged.
Interposers contain routed clines and bond fingers, normally. The fingers provide a point for bond wires coming from dies mounted above the interposer to connect to. The routing clines then connect these fingers (normally located closer to the center of the interposer) to a second set of fingers (normally around the periphery of the interposer). A second set of bond wires will connect from these peripheral fingers down to the package substrate or to another die/interposer lower down in the stack. This helps to reduce the length of bond wires (and amount of gold/copper needed for the wires) and minimizes the length of the span of the wire over a lower die in the stack that might extend a significant distance out from the edge of the die mounted above.
When you use these items will depend upon your specific flow and design requirements, however. I can't tell you when you will add them to your design. All I can say is that the more accurate your design, the more accurate the SI extraction, 3D view (and 3D bond wire DRC checks), etc. will be.
In reply to Tyler:
So how exactly do you create a spacer in the SIP tool? I tried following the help files, but didn't get very far. Is a .dra symbol created first, then saved off as something else? I tried every different way that I know how.
Thanks in advance
In reply to vkess:
There is both a text document solution, as well as a video walking you through spacer and interposer creation in the self-help area. I don't have exact links to them, but they should be reasonably easy to find with a keyword search.
Or, if you just want a basic, rectangular spacer, you can create it dynamically in SiP 16.6 from the Add -> Spacer form by specifying the material, thickness, size, etc.
Ah.....found it and got it to work. Thanks for your help Tyler