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The System Connectivity Manager currently does not support the creation of a user defined Bus type. In the SPB 16.0 release, a new set of Electrical Net and Physical and Spacing Net classes have been added to the Constraint Manager. Prior to SPB 16.0, a 'bus' could be created in Allegro PCB Editor CM, but not in Design Entry HDL CM or SCM. There was also confusion (and possible conflict) between logical buses created in the schematic and user defined 'buses' created in the backend. In SPB 16.0, groups of buses, Xnets, nets, diff pairs can now be assigned to a Net Class. Going forward, a Net Class (which is supported in both the frontend and backend) should be used to create a user-defined grouping of signals.
Sourcelink now has a series of tutorials that describe the new features available in the 16.0 Constraint Manager (http://sourcelink.cadence.com/docs/files/Training/spb160/pcb_cnsmgr.html).