Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
The pictures just show some Chinese writing (I assume it'sChinese) and "pp.sohu.com". It is possible to add pictures as attachments (one per post) on the Options tab when posting a reply.
So without more detail, it's hard to know what the problem is.
Figure 1 is as below.
In reply to xxgenerall:
Figure 2 is as below.
Because the Q is so high, the lack of timesteps in a default simulation means that it will not be able to properly see the effect of the resonance.
By forcing more timesteps, you can see the amplitude decreasing (but it's rather slow, because this will clearly have a long time constant).
I simulated this netlist:
//V0 (Vin 0) vsource type=sine ampl=10 freq=159.154943K mag=10L1 (Vin Vout) inductor l=1uC1 (Vin Vout) capacitor c=1uR0 (Vout 0) resistor r=100K//ac ac start=159.154K stop=159.156K step=.001ac ac start=155K stop=160K step=.001tran tran stop=1 method=traponly maxstep=1/(2000*159K)
That number of timesteps is probably excessive - and I didn't wait for the simulation to end. If you look at the AC response, you can see that there's a very high Q on the resonsance. Looking at the beginning of the simulation (78million timepoints so far) shows the attached curve (obviously you can see the envelope).
In real life there would be some non-idealities in there...
In reply to Andrew Beckett:
Hi Mr Beckett,
Thanks for your help.
After reading your advise, I carried out 2 simulations again.
The first simulation is carried out with maxstep=1/(100*159K), as the original simulation setting. And, the second simulation is set up with maxstep=1/(2000*159K), following Mr Beckett's advice.
The figure of simulation results is as below.
It can be seen that, the simulation result is correct when maxstep=1/(2000*159K), and is wrong when maxstep=1/(100*159K).
The symbols are all turn on in the simulation result figure. It is indicated that, there are enough points among each Vout period, regardless of the maxstep value. So, I can't understand why simulation results are so different under the condition of different maxstep values.
Mr Beckett, could you help me please? Thank you very much.
It's quite hard to explain this without a long lecture on how circuit simulation works (as I usually give when teaching details about using Spectre efficiently and effectively), but essentially what happens is that at each timestep the simulator is solving the non-linear differential circuit equations numerically (using Newton-Raphson iterative methods). This solves the equations to a certain level of accuracy (controlled with various parameters, primarily reltol/vabstol/iabstol). So the result at any one point has some error.
Once it has a result for a timestep, the simulator will decide where it thinks it should take the next timestep. Assuming that it's decided a particular place (more later), it will construct a predictor curve based on previous timesteps - this is generally an adaptive quadratic equation - it depends a bit on the integration method, and whether there are breakpoints (discontinuities in slope, for example, such as you get with a pulse source), but in general it's a quadratic. It then solves the next timestep using the same iterative approaches starting from this predictor, and then compares the converged result against the predictor. if the difference is too high, it will reject the timestep and take a shorter one - this remaining error is called the "local truncation error".
The simulator uses the trend of the local truncation error to preemptively adjust the timesteps - it will relax the timesteps if the error is reducing, and tighten them if the error is increasing - the goal is to take as few timesteps as possible, but still follow the waveform accurately.
So at each timestep there are a few sources of error. With a driven circuit, these errors do not normally accumulate, as the driving signals correct for any errors made. With a fully autonomous circuit, the errors tend to persist - resulting in (effectively) numerical phase noise (in an oscillator).
In this case the circuit is driven, but has a resonance too - and the driving signal is dominating the response - and because of the high Q, the errors that are being made don't get corrected for. It probably would also get better if the tolerances were tightened, but by forcing a shorter timestep it has meant that the local truncation error is reduced and so it is better able to follow the very small changes from iteration to iteration which result in the amplitude of Vout decreasing.
You say that "there are enough points among each Vout period" - I don't know why you think that. Just because it looks smooth doesn't mean that a very small numerical error over a long time constant doesn't lead to inaccurate behaviour in such an ideal circuit with such high Q. Very high Q circuits, and in fact ideal circuits, are not that easy to simulate in time domain circuit simulators (not just spectre, but any simulator) because they really aren't optimized for that task. They are intended to simulate real world circuits in a reasonable time (but even then, oscillators can be tricky).
Does that help?
Thanks for your great help. I appreciate it.
Best wishes for you.