Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm simulating the jitter performance of a driven ckt (inverter chain like, e.g.). I'm confused by the simulation setup and like to ask a couple of questions regarding the setup parameters.
First I set sweeptype=relative and relharmnum=1 and run the simulation. Then I change relharmnum=0 and compare the output results from 2 simulatoins. It looks like that the difference is very small (smaller than 0.01fs). Per the Q&A from Cadence's support website, if we set relharmnum=1,we're looking at the frequency
from f0 + 1Xfstart to f0 + 1Xfstop (f0 is the fundamental frequency and fstart/fstop the sweep frequency range). 1 is the relharmnum.
I think this is the frequency range exactly of my interest. But I wonder why setting relharmnum=0 didn't really disable the sweep frequency range setting (fstart/fstop), if we just follow the equation as above. The small difference of simulation results show it.
I already explored the previous discussion regarding how to set fstop to simulate a driven ckt. The suggestion is to set it to 1/2 of f0 (fundamental tone frequency). It's consistent with Nyquist sampling theorem. But I like to know if it's in conflict with up/down conversion of noise whose frequency can be N times of f0 (N set by the maxsideband).
Thanks for clearing my questions and any comments welcomed!
I think you're just seeing the aliasing caused by the ideal sampler introduced at the output when you use pmjitter or tdnoise modes.
Consequently it only really makes sense to sweep up to f0/2 - you'll get noise from all sidebands folded into this band. It's not in conflict with the up/down conversion of noise in the circuit itself.
In reply to Andrew Beckett:
Thanks for your quick reply.
Also I like to know if my understanding to the "relharmnum" paramerter is correct?
In reply to eeask:
Actually, if you set relharmnum to k and the start and stop frequencies of the sweep to fstart and fstop, and your PSS fundamental is f0, then the pnoise sweep will be from:
k*f0+fstart to k*f0+fstop
So your "1*" were in the wrong place in your equation. Essentially the sweep is around the kth harmonic of the PSS fundamental.
But k=0 will cause the sweep frequency from fstart to fstop (eg. 10 to f0/2). It's nowhere close to any harmonics.
Just wonder why simulation results don't show much difference between k=0 and k=1.
An ideal sampler will alias the spectrum around all harmonics (including the zeroth) of the PSS fundamental. You'd expect to see the spectrum from 0 to f0/2 and then flipped from f0/2 to f0, then these two repeated between f0 and 2*f0, and so on.
Thanks again for your reply.
Based on what you mentioned regarding an ideal sampler introduced at the output in simulation, I have to ask another question. Let's take a simple example here:
fundamental freq=f0, fstart=10, fstop=f0/2,
the sampling freq of the ideal sampler=f0
This way won't cause any aliasing for the sampler at the output. (For the time being we just ignore any other harmonics.)
But If I'm interested the frequency at f0+f0/2+fx (fx is a freq that just makes the sampling violate Nyquist critera), the sampling at the output will NOT produce accurate result due to the aliasing.
Please correct me if my understanding is not right.
The noise which would have appeared at f0+f0/2+fx should appear at f0/2-fx