Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I am using multiplier (provided in ahdlLib library) to simulate the behaviour of mixer. One of the inputs (RF input to the mixer) is a sinusoid withh 100mV amplitude and frequency f_rf. The other input (LO input to the mixer ) is a square pulse with V_High =1 and V_low = 0 wityh frequency f_LO.
Multiplier gain is set to 1.
I am using PSS analysis (shooting method , errpreset set to moderate) to analyze frequency tones at the multiplier output.
Ideally I expect that multiplier will generate a frequency tone at IF frequency , f_IF= f_RF - f_LO with the peak amplitude given by
(2/pi)* (V_RF =100mV) .
Since I am using an ideal multiplier , I expect RF signal to be present at IF output of multiplier with exactly same ampliude (multiplier gain is set to 1 ).
But , I am observing loss through multiplier . Observed RF amplitude at the RF frequency was supposed to be 100mV but is 60.6mV and I am observing same loss for IF frequency.
To summarize : I am observing loss through ideal multiplier (gain is set to 1 ) when I try to use multiplier as a mixer . I am using PSS analysis shooting method to simulate the multiplier.
Please advise .
With Best Regards,
Are you using vsource (or vsin) as inputs, or port? It behaves perfectly (with vsource) in my case - I actually get half the peak amplitude at each tone (I'm not sure why it it whould be 2/pi). It's a voltage-based system.
Here's my netlist (easier than showing all the properties on the sources):
// Generated for: spectre// Generated on: May 29 18:42:13 2013// Design library name: RFworkshop// Design cell name: checkmult// Design view name: schematicsimulator lang=spectreglobal 0include "model/rfModels.scs"include "gpdk446.v10/models/nmos1.scs" section=nominclude "gpdk446.v10/models/pmos1.scs" section=nominclude "models/npnStd.scs"include "SpectreModels/RFmodels.scs"// Library name: RFworkshop// Cell name: checkmult// View name: schematicI0 (lo rf _net0) multiplier gain=1V0 (lo 0) vsource type=sine freq=1G ampl=1 fundname="LO"V1 (rf 0) vsource type=sine freq=900M ampl=1 fundname="RF"R0 (_net0 0) resistor r=1KsimulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf pss pss fund=100M harms=20 errpreset=moderate annotate=statusmodelParameter info what=models where=rawfileelement info what=inst where=rawfileoutputParameter info what=output where=rawfiledesignParamVals info what=parameters where=rawfileprimitives info what=primitives where=rawfilesubckts info what=subckts where=rawfilesaveOptions options save=allpubahdl_include "/export/home/apps/IC615_isr/tools/dfII/samples/artist/ahdlLib/multiplier/veriloga/veriloga.va"
And attached is the picture of my results.
In reply to Andrew Beckett:
Thanks for the quick reply.
I am using voltage sources as input . With two sinusoids as input, I am getting correct output. I made two silly mistakes while using multiplier. First was with vpulse source. I assigned v_high=1.2 when I should have assigned v_high=1. I was calculating gain as 2/pi when it should have been 1/pi ( upconverted and downconverted product). pi comes into picture when digital pulse is expanded into fourier series.