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I am a newbie to cadence and want to understand output log of cadence well. I attached an image of output log as it appears during transient analysis. Is it normal to get such a message ? Can you please explain how to verify if my circuits violates any of the above conditions ?
All this is telling you is that there are some assertions (device checks) defined in your model files, and that they are all turned on. Depending on the value of "checklimitdest" (on the Simulation->Options->Analog form), you can control whether the violations get reported in the log file, in a separate file, or in the PSF results (can be both the log/external file and PSF). If saved to PSF, you can access them via Results->Violations Display, but also by looking in the results browser.
Precisely what the device checks are for is dependent upon the implementation in your models. Hopefully somebody has documented them...
In reply to Andrew Beckett:
Thank you for your answer Mr. Beckett. I see "Vbs-Vds getting forward biased " warning in my output log for transient simulations. Is this a problem to my circuit ? I have attached an image showing it.
In reply to Sai Goutham:
If a diode is being forward biased, that's probably not a good thing, since it means you'll end up having current flow through the bulk. But whether this is real depends on the implementation of the check - and that's specific to your technology. You should consult the documentation for the models, and if it's not covered there, you should ask whoever provided the models or whoever implemented the checks.
Not really something I can answer reliably without visibility of the design and your models.