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I am trying to run a PSS analysis of a closed-loop PLL in spectre, but encounter converge problems.
Is it possible to run a PSS analysis of a closed-loop PLL?
Yes, this is possible - but it can be difficult if you have a large divide ratio. It's also only possible for integer-N PLLs (not Fractional PLLs).
See some discussion of this in Predicting the phase noise and jitter of PLL-based frequency synthesizers
In reply to Andrew Beckett:
thanks, Andrew. I managed to simulate s-domain model of closed-loop PLL. But now my PLL is formed as follows:
ideal PFD&CP, Loop filter and divider model written in veriloga language;
implimenting real VCO schematic.
And I am trying to run a PSS and Pnoise analysis of this PLL to estimate the VCO's pnoise contributition, but always failed in PSS analysis. simulation log shows that Converge problems exits.
I also run a trans analysis of this PLL. The result shows that the input voltage of VCO has small ripples when PLL is locked. The ripple voltage is 400uVpp. Is it the reason why PSS analysis has converge problems?
In reply to reddevil011:
> The ripple voltage is 400uVpp. Is it the reason why PSS analysis has converge problems?
I do not believe this has any bearing on your convergence issue. The ripple on the control voltage is expected and totally normal. Perhaps you might try running a PSS analysis of the VCO at the control voltage at which it locks, separately determining the loop bandwidth (since you can determine the Kvco and you note you have done S domain analyses), and using the phase noise of the VCO, determining its resulting contribution to the output phase noise of the PLL as a function of frequency. Since you mention that the non-VCO components are all ideal, the only other output contribution to the PLL phase noise will be the deterministic jitter associated with the magnitude and frequency of the control voltage "ripple".
This might help you get an answer with less trouble....but is only a thought after reading your post.
In reply to smlogan:
One other thing to consider is that you need to simulate the PLL as a driven circuit (i.e. not an oscillator). The fundamental frequency would be your input frequency, and the oscillator output is a harmonic of the input frequency.
If however the variation in the VCO input has a longer period than the input frequency, this may mean that there's a dead-band in the PFD (see Ken's paper that I mentioned earlier) - or it may just mean you need to give the PSS fundamental as a sub-harmonic of the input (but this will only work if the ripple is co-periodic with the input frequency).
It can be a challenge to get a whole PLL to converge in PSS. You almost certainly need to set the tstab so that it has locked, and even then it can be challenging. I don't see many people trying because of these challenges (and often I see fractional PLLs being used nowadays, and so you're scuppered because they're not periodic).
Thank you for your note, Shawn.
It is the conventional way to analyse Pnoise of seperate parts and get Pnoise of PLL using S domain transfer function. But right now I just want to analyse the closed-loop PLL in Spectre and verify the results with S domain analysis results.
I've set the analysis engine as "shooting", tstab large enough (verified with trans analysis) and fundamental frequency equals input frequency. I will try to check the other issues you mentioned.