Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm new to ADE XL and I encountered a problem when running Monte Carlo "Mismatch" only analysis (using IC61 and mmsim07.2). At the end of the simulation it always gives this error: Statistical results for Monte Carlo simulation are not available for the test. I checked the sim log file, it shows the simulation had no error, but it seems like for some reason the results are just not available.The "Detail" field in "Show Mismatch" window shows only "N.A.".
Could this be due to some set up issue in ADE XL or the PDK model (IBM) i am using? I did go through IBM's reference, and their subckts do have mismatch models, I also have set the global switches in .scs file to enable mismatch.
Can anyone help me on this? Thank you very much!
You didn't mention which IC61 version you are using. However, can you put the following line in your .cdsinit file -
envSetVal("adexl.monte" "dumpMismatchParameters" 'boolean t)
and then run the simulation.
Otherwise you can add any scalar expressions/measurement(s) in ADE-XL setup and then run the simulation. In this case the Monte Carlo data file will get generated even if the 'dumpMismatchParameters' option is set to 'nil'.
In reply to Ashish Patni:
Thank you so much for your reply. Adding an expression did get rid of that error. But I figured out why the mismatch analysis didn't work. The IBM model doesn't support the "Mismatch" only for Monte Carlo in Spectre. I have to choose "All", and turn off the process variation switch in .scs. It works now. Thank you!
In reply to Mike Tian:
I have the similar problem. I am using the cadence 18.104.22.1680.6 with AMS4.01 design Kit. When I try to run the monte carlo simulations it takes so long time to run to end compared to a single run although mc run number is 5. And when it finally ends, it gives warning as follows:
ADEXL-5052: Monte Carlo run stopped because no statistical data generated for the test_sim:simple_mc:1
How do you turn off the process variation switch (?) in .csc file ?
In reply to Hazo:
Do you have any expressions in your ADE XL output which are producing scalar measurements? My guess is that you are not measuring anything and hence get no resulting statistical variations? I don't really understand why anyone would need to "turn off the process variation switch in .scs file" - you can control whether it does process, mismatch or both from the UI.
I don't know what PDK you are using, but in my case, I'm using IBM 45nm and they do not support "mismatch" only MC simulation in spectre. So I have to turn off the process variation by changing the variable mc_global to 0 in .csc file. And run "all" MC sim to get mismatch at a certain corner. If you are using other PDKs there should be explaination in model manual or in .csc file.
I also encountered "non statistical data generated" error. Adding an expression at output would help with that.
In reply to Andrew Beckett:
I am getting same results even I have added the expression: sqrt(VDC("/net3")) to ADE XL.
Please file a service request so that this can be investigated properly.
I also have a similar problem.
I am using Cadence 22.214.171.124b.500.12 with the newest X-Fab 0.35µ XA035 PDK and whenever I try to start a Monte Carlo analysis ind ADE XL of a custom IC contructed with this technology I get the error message:
ADEXL-5052: Monte Carlo run stopped because no statistical data generated for the test
I followed the step for step guide provided in the Cadence help but still could not get the analysis to run.
Is there any solution or tutorial yet to get the Monte Carlo analysis to run succesfully?
In reply to MarkusN:
In reply to SahelA:
Usually this is simply because you are not including the statistical models. Without knowing the specifics of the model files, I'm not sure how anyone can help - probably best to go to the foundry supplying the design kit.
I've not tried running this in ADE XL (I had to throw something together to replace the veriloga model since I didn't have that), but I suspect that the problem is due to this:
subckt p_mos D G Sparameters W=10.0 L=5.0 F=5.0 NC=2 deltaVfb=0...
The bit in red probably shouldn't be there. The idea is that it is the global parameter which has the distribution (and mismatch then ensures that the variation is done per subckt instance). With this here (and it depends a little on how p_mos is instantiated, which I don't know from your example), the chances are that there is no distribution at all in this parameter, so it sees no statistical variation.
I'm not sure about the mps error - what subversion of the IC tools are you using (type getVersion(t) in the CIW), and which subversion of the simulator (this will be listed in the simulator output log files near the top)?
Also, I'm assuming you were running "mismatch" and not "process" (or both) since your models only have mismatch variation.