Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I do fft(using dft with N=1024 and set the input freq=100M*17/1024 ,strobperiode=10ns and simulation time>10240ns) on the output of the sin wave,and see that the noise floor is about -100db i repeat it for variuos step(strobperiode) and simtime but the noise floor doesn't vary more,I'm so confused that how can test the high resulotion adc with this low resolution wave,is the way to solve this problem
If I simulate this simple netlist:
//v1 (sinout 0) vsource type=sine freq=100M*17/1024 ampl=1r1 (sinout 0) resistor r=1Mtran tran stop=10240n strobeperiod=10n
Then I get the attached picture (which as you can see has very low numerical noise floor). If you're simulating a more complicated circuit, it may be the simulator accuracy that is limiting you - have you set errpreset on the tran analysis? Have you set reltol? Without knowing quite what you're doing, it's hard to be sure.
Hi I simulate a simple switchcap circuit (transmition gate with a cap and sin source)and when I take fft from the input side I obtain this,but i dont set any other options like you say.
In reply to Medya:
Hi again,I simulate the circuit that you were simulated it,but my FFT dont chang,what is the difference????can yuo tel me what is the other options value that you set in your simple simulation?thanks a lot.
The spectre version is 5.10.41_usr6.081308 and virtuoso ADE is 5.10.41_usr6.127.29.here are the input and netlist files of the simulation.
First of all, that's a rather old version of the simulator. When using IC5141, you should really use spectre from the MMSIM stream (e.g. MMSIM10.1 or MMSIM11.1) because spectre in IC5141 was superseded by spectre in MMSIM in late 2004, and has had no significant changes - over the last few years it has had no changes at all - even in the latest hotfix of IC5141 it's from December 2008.
I simulated using a slightly later version of spectre (22.214.171.124508 - so 4 months newer), and plotted the results in the latest version of IC5141 ( 126.96.36.1990.6.151 - which dates from November 2011), and I see the same results as I did in IC615/MMSIM11.1. See the attached plot (from wavescan) - I get the same results with the older AWD calculator/waveform tool.
As I asked before, how did you plot the FFT results? You mentioned in another post that you were generating a csv (how?) and so I'm wondering if you were doing the FFT in some other tool (Matlab, maybe?)
In reply to Andrew Beckett:
By the way, I've just noticed your screen grab from your switch cap circuit (I didn't see that yesterday because I was only replying via email from a hand-held device). I'm wondering whether you've just not given enough time for the circuit to settle and hence you have not got a true period - maybe you need to give it longer and then take the last 10240ns for the FFT.
That wouldn't explain why you don't get good results with the simple sine-source only though.
Thank you alot Andrew,
finally i have to run the fft analysis(.csv from tran output) with matlab code that i tested it before,(I use the table option in graph window for extracting .csv), but when the .csv data is used for calculating sfdr and sndr I noticed that the noise floor was very large,so I used the dft function for comparing and know what was the exact noise floor for ideal sin in this circuit but the results wondered me.then use simple circuit(that you used),in this case the result dont like to yours,too.Now, I dont know waht is the problem ,Is it from simulator or from mistake in doing fft with wrong number of samples?what is your idea?
But you've still not said precisely what you're doing when you get the erroneous results (from the simple sine wave case)...
As I said before, the best bet would be to log a service request for this.