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I have instances of a subcircuit< say, ABC> in different blocks of my design. But when i created netlist, the port mapping is correct only in one block.
Three main blocks are AAA, BBB and CCC. I used ABC in AAA, BBB and CCC. But when i created netlist, the port mapping for ABC is correct only in AAA. In BBB and CCC, it is not showing all the ports of ABC.
So, i couln't make my design LVS clean.
Please tell me how to solve this.
Thanks & Regards,
I think you should update the CDF of the subcircuit ABC. You can just
re-create the symbol view form the scheatic view, the CDF will update
automaticlly. Hope this can help.