Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I get the following errors while running DRC using diva:
error: Illegal keyword downup found in geomsize().
1288 met1SlotWGT3 = geomsize(Met1_slot 1.499 downup)
error: unknown symbol(unselected) .....
*error* : eval :undefined function -geomSizeAnd
I get a lot of these errors for different metal layers and poly. Checked the divaDRC.rul file. These statements are in there. Am not sure if i shud delete these of let them be as it is.
i am using version 5.1.0, subversion 220.127.116.11
Also i am using a 130nm library, i dont think that shud matter though. I tried contacting the fa, they tell me its not an issue on their end.
Please help as i have been stuck with this issue for over two months now
If that's the exact text, looks like a typoin the rules to me. Capitalization matters so it should be 'geomSize' not 'geomsize'.
In reply to aplumb:
sorr, it was my mistake .. i typed the whole thing in, the 'S' in geomSize is capitalized in the divaDRC.rul file. My suspision is that i might be using a much older version of cadence. what do you think.
In reply to manavraina:
You are running the first release of IC5141, very old, from 2004. The documentation I have access to does not go back that far. I would assume that the command did not get those additional arguments till later, I know that unselect was added after USR4.
Usually if you ask the fab, they will tell you on which software release they tested their design kits. I suspect they were using a much later USR for that release.
I would update to the latest USR to make sure that the command you are using is complete.