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After I synthesize a design I made and look at the timing report, I see that the critical paths all go through clock buffers. This seems strange to me because the path through the clock buffers should be roughly equal for all paths and the only difference should be skew or jitter. The path going through the clock buffers is adding a decent amount of delay to the design. Does anyone know what I'm doing wrong or how to fix this? I have pasted the beginning of the path below.
+-------------------------------------------------------------------------------------------------------------+ | Instance | Arc | Cell | Delay | Arrival | Required | | | | | | Time | Time | |----------------------------------------------------+-------------+-------------+-------+---------+----------| | cpu_inst/clock_select/clock_state_machine/U12 | Y ^ | | | 0.000 | -2.945 | | cpu_inst/system_clock__L1_I1 | A ^ -> Y ^ | CLKBUFX6TS | 0.323 | 0.323 | -2.622 | | cpu_inst/system_clock__L2_I1 | A ^ -> Y ^ | CLKBUFX4TS | 0.229 | 0.552 | -2.393 | | cpu_inst/system_clock__L3_I1 | A ^ -> Y ^ | CLKBUFX4TS | 0.315 | 0.868 | -2.078 | | cpu_inst/system_clock__L4_I1 | A ^ -> Y ^ | CLKBUFX6TS | 0.337 | 1.205 | -1.741 | | cpu_inst/system_clock__L5_I1 | A ^ -> Y ^ | CLKBUFX6TS | 0.322 | 1.526 | -1.419 | | cpu_inst/system_clock__L6_I1 | A ^ -> Y ^ | CLKBUFX6TS | 0.231 | 1.757 | -1.189 | | cpu_inst/system_clock__L7_I1 | A ^ -> Y ^ | CLKBUFX20TS | 0.210 | 1.967 | -0.978 | | cpu_inst/system_clock__L8_I1 | A ^ -> Y ^ | CLKBUFX20TS | 0.266 | 2.234 | -0.712 | | cpu_inst/system_clock__L9_I3 | A ^ -> Y ^ | CLKBUFX20TS | 0.268 | 2.501 | -0.444 | | cpu_inst/system_clock__L10_I7 | A ^ -> Y ^ | CLKBUFX20TS | 0.266 | 2.767 | -0.178 | | cpu_inst/if_rd_rs_dec_addr/\loop.scan_cell /q_r | CK ^ -> Q v | EDFFHQX8TS | 0.426 | 3.194 | 0.248 | | eg | | | | | | | cpu_inst/if_rd_rs_dec_addr/\loop.scan_cell /U5 | A v -> Y v | BUFX20TS | 0.167 | 3.360 | 0.415 | | cpu_inst/rd_inst/regfile/U243 | A0 v -> Y ^ | AOI22X4TS | 0.356 | 3.716 | 0.771 |
This is the Custom IC forum so we probably cannot answer your question. Please take it the Digital Implementation forum to get a better answer.