Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Look at sourcelink solution 11017972 - this gives a component "deepprobe" which allows you to do this for spectre.
In reply to Andrew Beckett:
In reply to Pramod:
I am not able to find this sourcelink '11017972'. I am also not able to find any discussion thread explaining how to use this 'deepprobe'. Kindly help & direct me to the corresponding source of explanation.
In reply to N Venkat:
Log in to support.cadence.com and search for deepprobe.
How do we handle arrays? We get an array when we try to access a node within an instance like
In reply to swdesigner:
I presume you are saying you are getting an "error" (not "array") when you are trying to use deepprobe with such a net? First of all, you need to find out what that net is called in the netlist, becaue the parameter for deepprobe is the name in the netlist. If in IC61, you may have the net shown as Xcell\<3\>, in which case you might have to enter (I think) Xtop.Xnest.Xcell\\<3\\> (i.e. two backslashes) because otherwise one will get escaped. Not 100% certain (and I'm afraid I don't have time to make the experiment). Anyway, experiment around this and see what happens.
Right on both counts. Thanks.
is how you handle a bussed net within an arrayed instance.
Would this work with AMS or, as the doc says (currently), only for spectre?
What would the workaround be to get it to work with AMS-APS?
I'm using IC5141ISR20110503, MMSIM22.214.171.1241.isr6, and INCISIV12.10.3
I have been able to get deepprobe to work with AMS(APS) using OSS through the ADE, however it requires modifying the resulting netlist.vams located in the simulation's "netlist" directory. The toplevel netlist located in the netlist/ihnl/cds* directory has an iprobe line:
_ANALOG_BEGINx1 (x0.n0 n1) iprobe_ANALOG_END
However when this makes it into the netlist.vams file, which is what AMS uses when running, it looks like:
iprobe x1 (\x0.n0 , n1);
The hierarchical name has a \ placed at the beginning of the name which causes it not to work. Deleting this \ and rerunning without renetlisting allows the net to be accessed hierarchically. There may be an option to stop this \ from being added, but I don't know what it is. Until then, hand editting is a reasonable approach.
In reply to jjcan:
Hand editing is to be deprecated as much as possible.
Cadence gave me a solution a couple years back. You can place a deepprobe whose property form has 2 fields - one the hierarchical pathname for AMS and one for Spectre. It works good..
I've searched for "deepprobe" and I haven't found this solution. I
don't know where to start since I haven't found anything that describes
how a hierarchical pathname for AMS differs from Spectre. I've found
hints that this may be the case, but not what it may be. So, what is
Attached file will work for IC6.
RENAME to deepprobe_OA.tar.gz and then do tar -xzvf, etc..