i am using cadence virtuoso to simulate some cmos circuit, in which there is inverters chain with tapering ratio of T. But When I increase the w/L ratio to a certain level, the simulation error incurred, saying the effective width is less than zero.
I am using IBM 30nm process and I couldn't found any model relating to modulation of the width.
Can anyone help me on it ?
Check the lmin and wmin set inside the model. Probably one of them is blowing up as you are tapering your W/L values.