Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I need to have a precise estimation of the parasitic capacitances of my MOSFETs, used as switches. I was thinking, for the measure of capacitances to impose a voltage source with voltage Vs increasing linearly with time and measuring the current (proportional to the capacitances). So Vs=K*t. For example connecting the generator to the gate, and the other terminals to ground, I could measure the Cgd and Cgs. Is it a good method?
Thanks a lot,
I have the same problems. I want to design a buffer chain. According to the design procedures from the book by Baker, I need to know the input capacitance of the inverter and the output capacitance of the inverter. What I try to do is do the DC analysis in cadence, then print the dc operating opoint. After that, we can see a lot of parameter listed in the table.
However, I felt a little confused. If the input capacitance of the cmos inverter is considered, cin equal to cgs,nmos+ cgd,nmos+ cgs,pmos,+cgd,pmos and cout= cdb,nmos+csb,nmos+cdb,pmos+csb,pmos + the input capacitace of next stage of inverter link.
Is that right?
From the results of the simulator, cgs is not equal to csg. Both of this two values is negative. Should I just ignore the negative sign and which value I should choose?
In reply to IanX:
I have the same problem. I have search all over the web, thesis, forum, etc and I just can't reach a conclusion. I read that one coud use the print OP and use those values, I read that one should use transient/AC analysis to get a more accurate value however this was contested by some user in the forum that I read that, and so on.
The feeling that I have is that:
1st. People doesn't want to share how this is done;
2nd. No one knows and they are just commenting in forums;
I need to design a chain of inverters (drivers) to drive my power devices and I don't have any starting point.
Regarding the negative capacitances, that is related to the way the spectre/bsim model does the math. My problem is to know if we can ignore that "minus" sign in order to use the capacitance that we get from print OP (if this is the way to get the capacitances).
Taking the advantage of this post, I'd like to know if someone can tell me:
1st. How can I get the Kn,p value? (I know that Kn,p = un,p Cox and for that;
2nd. How can I estimate the Cox? From the technological documentation I have access to the extracted Tox from the foundr. I can use this value and the respective known equatio to get the Cox? This leads to;
3rd. If I can do that, then I can estimate the capacitances using the Cox and the basic equations do compute the Cgs, Cgd, Cgb etc?
Hope get some answers here....
I would approach your issue slightly differently. If you need to determine the input and output capacitances of an inverter, I would simulate the input and output capacitances directly as a function of inverter DC operating point and at a particular frequency. I have a test bench that I use quite frequently to determine the input impedance our output impedances of either devices or larger blocks (switches, buffers, etc.). The test bench applies an AC current to the device under test. A DC voltage is impressed to the device under test using a large inductor. The voltage across and current to the device are measured in an AC analysis, and at a particular frequency, the input reactance is computed to determine the input capacitance. This method avoids the complexities of using BSIM model paramters to determine input and output capacitances of blocks. It also highlights the very significant impact of such things as Miller capacitance, parasitic routing capacitances (if used with the extracted view of a block). I hope this is useful to you.