Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I am new to this community. Let me introduce as Debjit from India. I am facing the following problem.
I want to change the method of integration and/or the errpreset of a simulation during run time. I am able to change the reltol, vabstol, iabstol value during runtime by tcl commands like "analog -reltol" etc. Does there exists some tcl commands to change the method of integration or errpreset?
I am using the following version of the Cadence Setup.
ICFB : 220.127.116.110.6.141 Spectre Version: 18.104.22.168.isr4 NCSIM version: 09.20-s014
Thanks and Regards
From your description, it sounds as if you're using AMS Designer as the simulator (probably wise to actually say that, to avoid guesswork on the part of anyone who wants to try to help you). In which case the version of spectre is not relevant, because it's just using the simulator from the INCISIV92 stream.
Anyway, the Tcl analog command only allows you to change iabstol, reltol and vabstol (and the analog stop time). There is no Tcl command to change errpreset (which is dominated by the three above anyway) or method. You could probably use the save/restart options to stop the simulation at a particular point, change the analog control file (hence changing the errpreset or method) and then restart with that. Need to take a little care in case you introduce a step at that point.