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I am using a generate statement to instantiate a delay module (cur_starved_delay) 11 times. The basic idea is to model a 11 stage ring oscillator using current starved delay cell. But i get syntax error in generate statement. Can anyone help me with this. The code is attached below.
module multiphase_vco(Vbias_p,Vbias_n,Vdd,Vss, out);parameter integer NO_STAGE = 11;parameter real C_load = 1e-12;parameter real Kp = 1;parameter real Kn = 1;parameter real Vt = 0.2;parameter real pos_tol = 0.2;parameter real neg_tol = -0.2;
genvar i;input Vbias_p,Vbias_n,Vdd,Vss;output [11-1:0] out;voltage Vbias_p,Vbias_n,Vdd,Vss;electrical [NO_STAGE-1:0] out;real ph_out[NO_STAGE-1:0];generate for (i =1;i<=11;i=i+1) begin cur_starved_delay #(.C_load(C_load),.Kp(Kp),.Kn(Kn),.Vt(Vt),.pos_tol(pos_tol),.neg_tol(neg_tol)) D_i(.Vin(ph_out[i-1]),.Vbias_p(Vbias_p),.Vbias_n(Vbias_n),.Vdd(Vdd),.Vss(Vss),.Vout(ph_out[i])); endendgenerateph_out = ph_out[NO_STAGE]);@(initial_step) begin ph_out = V(Vss);endend endmodule
Please ignore the extra end statement after initial_step block
In reply to write2rammy:
In fact it's not just the end statement that's wrong. The whole:
ph_out = ph_out[NO_STAGE]);@(initial_step) begin ph_out = V(Vss);endend
is wrong. The first line has got an extra close parenthesis. It probably needs to be inside an @(initial_step) block, or similar, in which case it's superflous. Also, these need to be inside an analog block.
Next is that the D_i instance appears to be connecting to a real array, rather than a voltage array.
Finally is the main issue, that assuming that cur_starved_delay is an analog module (you didn't give the details), this is not supported in AMS. If I omitted the lines above, it compiles OK with no errors, but during elaboration I get:
D_i(.Vin(ph_out[i-1]),.Vbias_p(Vbias_p),.Vbias_n(Vbias_n),.Vdd(Vdd),.Vss(Vss),.Vout(ph_out[i])); |ncelab: *E,VHANAG (./gencode.v,38|19): Module "cur_starved_delay" has analog element(s) in it. Instance multiphase_vco.genblk1.D_i of this module is not yet supported inside generate statement.voltage Vin,Vbias_p,Vbias_n,Vdd,Vss,Vout; |ncelab: *E,VGDADS (./gencode.v,6|10): multiphase_vco.genblk1.D_i.Vin has got declared analog discipline "voltage". Use of analog element inside Generate statement is not yet supported.voltage Vin,Vbias_p,Vbias_n,Vdd,Vss,Vout; |and many such errors. If I expand these errors with nchelp I get:
UNIX18> nchelp ncelab VHANAGnchelp: 09.20-s020: (c) Copyright 1995-2010 Cadence Design Systems, Inc.ncelab/VHANAG = The module/architecture pointed out by this error message has analog element(s) inside it. Instantiation of this analog unit inside a Verilog or VHDL generate statement is not yet supported.UNIX19> nchelp ncelab VGDADSnchelp: 09.20-s020: (c) Copyright 1995-2010 Cadence Design Systems, Inc.ncelab/VGDADS = The net pointed out by this error message is declared as analog. Use of this analog net inside a Verilog or VHDL generate statement is not yet supported.
You will need to contact customer support and request an enhancement to support analog elements inside a generate statement. There is already a request for this, CCR 700708, but it's best if each customer requests it who needs it, then there's a fair reflection of the amount of demand, which helps in prioritization.