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I would like to know about the correct flow for mixed signal design. Assuming now I have all my analog blocks readily verified in spectre, and the layout of the analog blocks pass DRC and LVS check. My digital blocks ( e.g state machine) layout are obtained from the place and route tool ( Cadence encounter). If I want to verify the system which consist of both analog and digital circuits, should I stream out the digital blocks layout into Cadence Virtuoso to combine both digital and analog layout together, then run DRC and LVS again, and extract the parasitic and rerun the whole system simulation ? But I am wondering will it take me a very long time to run the simulation as the digital blocks might consist of quite a number of gates.
I have run AMS simulation by combining the analog blocks and VHDL code together. But I am not convinced by the simulation result as the behavioral VHDL code and the analog circuits does not seems represent the actual circuit behavior after laid out ( parasitic, fan out effect etc).
Thanks in advance.
Hi hon cheongYour flow is correct. It is actually quite common to perform final integration on Virtuoso platform using gds from P&R tool. For such simulations, we can use fastspice simulator ultrasim. Ultrasim also has parasitic reduction feature to further reduce simulation time. You can of course also do parasitic reduction during QRC extraction.Best regardsQuek
In reply to Quek:
Thanks for the useful information.
I have another issue regading the mixed signal design flow. Currently I am in a university, and access the IBM 130nm process through MOSIS. The standard cell GDS file is not provided by ARM. Is it possible to integrate both analog and digital layout together without the standard cell GDS file? I think it would be impossible for me to do DRC and LVS check without GDS file, is that true?
Thank You .
In reply to hon cheong:
Hi hon cheongIt is indeed not possible to do drc and lvs check without the standard cell gds.You need the gds file. Integrating with standard cell gds would be quite meaningless because the gds file from the P&R tool would give lots of missing cell errors when imported into Virtuoso.Best regardsQuek
Thanks for the reply.
However, I am informed by MOSIS that no GDS file would be provided. Some of my colleague who done full digital design tape out their chip without the standard cell GDS file, in which the standard cell GDS file would be inserted during fabrication.
Is that a way to verify my final circuit even without standard cell GDS file? Such as stream out the digital layout in other format? e.g DEF? I am not familiar with the streaming out methods available.
Hi hon cheongWithout the standard cell gds, you will have the make the assumption that the tech lef which you have used for routing in the P&R tool is in sync with the drc rules file. Any placement errors that might result in metal spacing violations would not be detected if drc is only run on the interconnects. A full lvs check would not be possible. You can however define the digital cell as a blackbox and do lvs on analog portion and interface of analog/digital cells. Just stream out the digital design and stream it into Virtuoso. Then remove the internal parts of the digital cell, leaving only the pins.Best regardsQuek
Hi Hon Cheong,
We have a mixed environment and we bring verilog gates into schematics and then run ams with SDF for simulation with analogue schematics
Although we use verilog it's likely with VHDL you'll find a verilog gates netlist in the encounter directory - import this using VerilogIn in the CIW - you will need a symbol library and verilog libraries. Things you may have problems with are busses, brackets, power pins etc. You should then be able to netlist and attach sdf in the elaboration stage of AMS(NC) - you'll need to compile the sdf using ncsdf. If you have enough licenses and a new version of IC5141( not sure about IC61) then also try the APS solver which will give you 2-3x performance with full spectre accuracy. Ultrasim is also available but be careful with accuracy in things like PLL's, VCO's.
Also we use DEF to import the design into Virtuoso rather than GDS - run defOut in encounter and Import->DEF in ICFB - you may need to clean things up by replacing abstracts and deleting blockages but shoud be OK. This way you can also LVS the whole chip
In reply to gmc99:
I'm also working along the same lines, and have two questions regarding simulation with this kind of mixed-signal flow. Lucky for me, I have access to the gds files, so I can run DRC and LVS on my full design in virtuoso. So no problem there. However, I'm hoping to use sdf back-annotation for digital cells and full spectre analog models for the rest. I've managed to do this in another technology node with Diva and the pearl mixed-extract flow, with everything running through spectreVerilog.
The catch is this : we don't have the DRC/LVS/Parasite extract rules for Diva or Assura. We have to use a 3rd party tool. It works well, and I can get standard parasitic formats (SPEF, DSPF, HSPICE), seperated in hierarchical sections if I want (ie, analog-only). So I thought about importing the SPEF in Encounter (with analog blocks as black boxes), and then get my .sdf file from there. I found the box where to tell AMS about the sdf file, too. But I'm stuck on how to pass the parasitic netlist to AMS for the analog blocks. I know that UltraSIM can attach DSPF files, but what about Spectre or APS? I've tried to look around the web, manuals and Cadence support, but nothing yet.
My second question is about .sdf generation in Encounter. I have done it before in version 8.1, and it worked great with the spectreVerilog, AMS and another 3rd party simulator. However, the same design produces a quite different sdf file in Encounter 9.1 (digital impl), where 1 field (the middle one) is left empty. Furthermore, I used the exact same .conf file and placement script, and the results are quite different. What am I missing?
(INTERCONNECT I_NCS U134/A (0.0037:0.0037:0.0037) (0.0037:0.0037:0.0037))(INTERCONNECT I_SCLK Q_TRANSACTIONCOMPLETE_REG/CKN (0.0045:0.0045:0.0045) (0.0045:0.0045:0.0045))
(INTERCONNECT I_NCS U134/A (0.003::0.004) (0.003::0.004))(INTERCONNECT I_SCLK Q_TRANSACTIONCOMPLETE_REG/CKN (0.000::0.000) (0.000::0.000))
Note : we don't have OpenAccess libraries, so I export/import my layout through DEF.
In reply to MzQuarter:
Hi MzQuarterParasitic file stitching capability is only available in ultrasim. Spectre and aps are not able to do it. Please use amsUltra for spef backannotation in mixed-signal simulation. COS solution 11607500 explains the method. Please post the Encounter question in our digital implementation forum.Best regardsQuek