In reply to jdgriggs:
Hi jdgriggsYour mos devices have been extracted as generic devices. Hence source and drain pins will not be automatically permuted. VXL layout pin permutation is not related to Assura LVS, hence it will not resolve the problem. You can resolve the problem as follows:a. In Assura LVS form, go to "avCompareRules"b. Select "Network"c. Select "swapPins" and add the following expression for schematic side:swapPins("pfet(Generic)" "(p S D)")d. Run LVSBest regardsQuek
In reply to Quek:
I am having an LVS problem and I noticed this post. I am not sure if anyone is still around (based upon the 2010 responses) to reply.
At the end of the lvs report I have the following message:
Preprocessing layout network phase 2*ERROR* Device 'pfet(Generic)' on Schematic is unbound to any Layout device.*ERROR* Device 'nfet(Generic)' on Schematic is unbound to any Layout device.*ERROR* UnBound devices found.Info: All devices must be bound or filtered for comparison to be run.Exiting nvn.
It implies that I have devices in the schematic which cannot be matched to a layout device. I have tried this in calibre and succeeded in getting a clean LVS; so I know the layout and schematic do match. I would like to have assura working as well. One possible issue is in the use of multiplicity; m>1 for every transistor in the schematic. The LVS checks using assura for devices which have m=1 have worked. Is it possible to fix this problem ?
In reply to bartman:
Hi AlanWould you please kindly start a new post for your issue? This thread has already ended in 2010. ThanksQuek
I created a new post this morning. But, I am not sure if I did it correctly. I am checking it now.