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Here is the lvs file
****** 5_ring_oscillator_1 schematic Ring_Oscillator_inv_sch_1 <vs> 5_ring_oscillator_1 layout Ring_Oscillator_inv_sch_1
Cell/Device schematic layout
(inverter schematic Ring_Oscillat...) Cell 5 5
(buffer schematic Ring_Oscillator...) Cell 1 1
(bufferx2 schematic Ring_Oscillat...) Cell 1 1
(mosvar) Generic 1 1
Total 8 8
================= Original Filtered
Cell/Device schematic layout schematic layout
(buffer) Cell 1 1 1 1
(bufferx2) Cell 1 1 1 1
(inverter) Cell 5 5 5 5
(mosvar) Generic 0 0 0 0
(mosvar_m0) Generic 1 1 1 1
================= Filtered Reduced
================ Total Unmatched
(buffer) Cell 1 1 0 0
(bufferx2) Cell 1 1 0 0
(inverter) Cell 5 5 0 0
(mosvar_m0) Generic 1 1 0 0
------ ------ ------ ------
Total 8 8 0 0
Match Statistics for Nets 12 12 0 0
====== Open Instance Connections ==============================================
Layout net: |I25/vdd should connect to:
Layout net: |I23/vdd should connect to:
====== Summary of Errors ======================================================
Schematic Layout Error Type
--------- ------ ----------
- 2 Open Instance Connections
In reply to jdgriggs:
Hi jdgriggsI think perhaps the lvs mismatch can be resolved by joining up the vdd rails of the 2 instances. : ) Best regardsQuek
In reply to Quek:
Hey Quek thanks for the reply..the rails are suppose to be separated it's the buffer stage that is causing the error... as indicated in by lvs error file.
Hi JGThat's right! Sorry that I had not looked at your schematic carefully. : PWould you please upload the following 2 ascii files and also the cls file?terminal>vldbToCdl design.lnn > design.lnn.asciiterminal>vldbToCdl design.snn > design.snn.asciiPlease upload the files, not cut and paste.ThanksQuek
Here are the files you requested
Hi JGThanks for the files. It appears that your nwells in buffer and buffer2 cells are not connected to the vdd rails. I thought that there might be something wrong with geomConnect section in extract.rul file but since the nwell of the inverters got the vdd connection, it seems to mean that Assura can see M1->cont->Nwell connectivity. This is indeed quite puzzling.Would you please upload a snapshot of the layout with only nwell, poly and cont layers?ThanksQuek
Here is the picture you requested also I included my LVS run files for the oscillator. It really is a mystery for me as well bcause I have done this design 5 times already and I come to the same impass.
Thanks for whatever insight you can provide.
Hi JG Thanks for the files. It appears that your nwells in buffer and buffer2 cells are not connected to the vdd rails. I thought that there might be something wrong with geomConnect section in extract.rul file but since the nwell of the inverters got the vdd connection, it seems to mean that Assura can see M1->cont->Nwell connectivity. This is indeed quite puzzling. Would you please upload a snapshot of the layout with only nwell, poly and cont layers? Thanks Quek
just wanted to follow-up on our conversation to see if you had any more insight
Hi JGThanks for the files. Unfortunately I can't find any more clues in the files too.It looks like it is better for you to file a service request to Cadence support for this issue.