Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I have a list of signals and corresponding strip numbers that I want to plot them on in a form like:
my_stripAssignment = list( '(v("/enable") 1) '(v("/disable") 2) )
my_stripAssignment = list( '(v("/enable") 1)
'(v("/disable") 2) )
I have a foreach loop that grabs the signals and their strip number assignment one-by-one:
foreach( signal_name my_stripAssignment plot( getData(car(signal_name)) ?strip cadr(signal_name) ) )
foreach( signal_name my_stripAssignment
plot( getData(car(signal_name)) ?strip cadr(signal_name) ) )
I noticed that if I query the signal_name during the loop that it no longer just returns the assigned value out of the list, but instead also has the resultsDir and result data along with it. In other words, I expected signal_name to return v("/enable") , but instead it returns v("/enable" ?resultsDir "/home/user/CDS/OCEAN/test/psf" ?result "tran").
So it seems this change happens after I use the getData command. Am I doing something wrong? Is there a better approach? Or is getData messing me up?
I don't think you are doing anything wrong; I think you are right that it is getData that changes the name. It is a pity that you cannot do this in a single call to plot, but unfortunately you need to expand the list of variables and so you cannot use the apply function to build the call to plot (in other words, you'd like to be able to do this: apply('plot `(,@listOfVariablesToPlot ?expr ,listOfNames ?strip ,listOfStripNums) - I think I've got the syntax right there, but I have not tested this, and it won't work anyway).
apply('plot `(,@listOfVariablesToPlot ?expr ,listOfNames ?strip ,listOfStripNums)
I think that you just need to add the ?expr argument to the call to the plot function so that the name is as you'd like to see it, here's an example:
foreach((sig num name)
plot(sig ?strip num ?expr list(name))
I have not tested this! You might need to rework it, and possibly use getData again?
Anyway, I hope that this helps you.
In reply to skillUser:
First of all, your example can't have worked - it had a quoted list which had v("/enable") in it, and then you were doing getData on the v("/enable") - so it would have failed. I presume it was more like this:
my_stripAssignment=list( list(v("net24") 1) list(v("net25") 2) list(v("net51") 3))first=tforeach(signal_name my_stripAssignment wave=car(signal_name) plot(wave ?strip cadr(signal_name)) when(first displayMode("strip") first=nil ))
Anyway, a better approach might have been to do this:
my_stripAssignment='( ("net24" 1) ("net25" 2) ("net51" 3))first=tforeach(signal_name my_stripAssignment wave=getData(car(signal_name)) plot(wave ?strip cadr(signal_name) ?expr list(car(signal_name))) when(first displayMode("strip") first=nil ))
Or better still:
my_stripAssignment='( ("net24" 1) ("net25" 2) ("net51" 3))newWindow()displayMode('strip)awvPlotWaveform(currentWindow() foreach(mapcar sigInfo my_stripAssignment getData(car(sigInfo))) ?stripNumber mapcar('cadr my_stripAssignment) ?expr mapcar('car my_stripAssignment))
Thanks for the reply. I had already done something very similar as my solution.
I suggest that the documentation for getData be reviewed to explain its behavior in situations like mine. :)
In reply to Andrew Beckett:
Normally Andrew, you are spot on, but in this case, you are wrong about my example. My example does indeed work, exactly as I have shown it.
Thank you for providing the alternatives, especially the last one, however, none of these really address the issue that getData seems to be modifying the argument provided to it.
In reply to SharksFan:
Well, I'm very surprised, because that would mean that your code was doing:
and that should not work (and did not work when I tried it). Still, I'm happy to be wrong, but I certainly would not want your code to depend upon this because it is not supposed to work, and is unlikely to be future-proof. It should be (of course):
Note that there is no bug here. When you call getData without the ?result or ?resultsDir argument, it picks those arguments up from the last openResults() call (or the results from the last completed simulation if you ran a simulation in the same session), and the ?result arg comes from your last call to selectResult(). The waveform object that it creates has the expression property set (on the y-vector) to the be the quoted function that created it. You can always override this by setting drGetWaveformYVec(waveObj)->expression=...