Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Is there any way to get the solution 11017972 - accessing a lower level net from the top-level - to work with AMS?
In reply to Andrew Beckett:
I'm working through the ADE - so I guess it's cell-based?
In reply to swdesigner:
Running with default, I have "Cellivew-based netlister with ncvlog, ncelab, ncsim" checked. I didn't even know about these options and what they mean.
I tried OSS, but it fails elaboration for another reason - complains about too many module parameters being passed to the verilog modules.
I'm on 18.104.22.1680.6.143
Any clues here? If I get a lead, I might be able to create the workaround myself - I guess I'd have to modify deepprobe.il and cdsinfo.tag?
As I use AMS intensively, it would really help my productivity.
Apologies - just been a lack of time for me to do my normal job as well as write the custom netlisting procedure needed for this to work in AMS Cellbased. It's completely different from the custom netlisting procedure used for spectre, so it's just a matter of me having the time to do this. Probably best to be done via a service request anyway.
I've been working with the AE who is handling this SR, and I managed to find some time to come up with some code to get the deeprobe to netlist OK for AMS (with the Cell Based Netlister). Once he has checked this out with you, I'll update the solution on Cadence Online Support to include the additional information.
That would super. I depend heavily on AMS...
Along the same lines, is it possible to create a component, somewhat similar to deepprobe, that can be used to create a voltage equal to a parameter of another component? Here's the motivation :
I want to trim an oscillator in my simulation - in a DC simulation. The oscillator freq is based on an RC time constant. Getting an R in an operating point sim is easy. Getting the C is not possible - you have to run a transient, which I'd like to avoid. If there were a component I could use - say param2volt that creates a voltage source with voltage equal to the C of the cap of interest, my problem is solved.
Did anyone try the deep probe (with or without the additional SKILL) with an OSS netlister?
I did manage to get it to work with Cell-view, but I recently changed over to OSS to support up-to-date features.
Whilst the simulation runs with the deepprobe, I get a warning during a transient run preamble, that the net
Testtop\.IDUT\.ITOP\.IADC\.fastreset doesn't exist.
The net to probe in my deep probe symbol refers to that net, but without the '\' characters. Why does it place those chars?
In reply to KMan11:
This works fine with the new "UNL" OSS implementation that is coming (it's currently under early adopter with a few customers), but there are no plans to fix it in the current OSS implementation (for reference, CCR 1089627). Unfortunately the translation code which translates spectre syntax to VerilogAMS incorrectly escapes the hierarchy delimiters.
That's a shame.....
ok...I'll continue to use 'force' 'release' statements to 'logic' discipline nets for now.