Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I have created a pwl source using the analog stimuli option for a particular pin.
The pwl source has many variables (like slew rate, amplitude etc) which is defined in my design variable section of the test.
When i netlist the test, it netlists fine, there are no errors.
But when i try to run a simulation, i get the error " *WARNING* asiiEvalDesignValList: problem with variable slew
*Error* in the Design Variables. AEL's message: data type error: cannot undefer "slew"
It feels like the analog stimuli are being read in before the design variables in some way, since in the design variables section i have the variable "slew" defined.
How should i overcome this error?
I forgot to add that all the variables in my pwl have the same error not just the slew.
In reply to rkic:
In the netlist, i do see all the parameters defined and the stimuli file being read at the very end, so my guess is that the parameters have been read in. So any ideas on what the source of the error could be? Do the order of the parameters matter? Should i first have the independent paraneters defined and then the dependant parameters?
I think I've only seen this being an issue when you have dependent expressions in rare cases. Anyway, there's a CCR, 715614, which talks about this - and it is planned (it says for an IC615 hotfix) - but I've not seen it actually be integrated.
I would suggest that you file a service request and reference this CCR number and ask for a duplicate to be created - ideally with a simple example which shows the problem. That will increase the likelihood of it being fixed sooner rather than later, and the AE can then see if there's a workaround in the meantime.
In reply to Andrew Beckett:
Thanks for your prompt reply Andrew. I will follow up.