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Is there a way to probe simulator as to the biasing conditions of a model implemented in verilog-a ? If not is this possible through verilog-a, via some kind of monitoring scheme or someone must go into spice netlist level? The simulator used is spectre.
It's not that clear to me what you're trying to do. What do you mean by "probe simulator as to the biasing conditions of a model..."? What does that actually mean?
Maybe you are talking about turning on the saving of internal variables - if so, this can be achieved by turning on saveahdlvars in the Save All form in ADE (or adding "mysaveopts options saveahdlvars=all" or "mysaveops options saveahdlvars=allwithnodes" to your netlist before simulating it).
In reply to Andrew Beckett:
Sorry for the bad description. What i would like to do is that depending for example on whether a node in my model has an ac source attached to it or a dc source attached to it, affect its behaviour. There are options for example for requesting $time $temperature and analysis("type") from spectre .Is there a way to probe from the model the spice netlist. i.e. something like if net#=vsin do something if net#=vdc do something else? If not could this be done automatically through SKILL/ other scripted way and redirect information inside verilogA somehow?
In reply to soathana:
That sounds a very odd thing to want to do, and I don't believe it's possible. I can't imagine why you'd ever want to do that...
Even using $analysis() should be used with caution.
Sorry for the late responce. I was on vacations. The thing is that I am impementing some aging effects on BSIM4, and they are partially dependent on past biasing conditions of the circuit. Anyways probably I think I will try with SKILL.