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I'm trying to instantiate this veriloga FET model http://ptm.asu.edu/postsi.html and i followed the instructions in the pdf to instantiate as a symbol. now when i try to run a simulation, I see the error:
ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'veriloga spectre cmos_sch cmos.sch schematic' for the instance 'I5' in cell 'tb_dc'. Either add one of these views to the library 'cntfet_sim', cell 'CNTfet' or modify the view list to contain an existing view.
I can manually descend into both the symbol and veriloga cellviews from the testbench, so I'm not sure what the issue is. All the forum posts I've seen seem to have solved the issue by adding 'veriloga' to both the switch view and stop view lists, which I have done - the software is just not seeing it.
can anyone help? I'm sure it's a simple fix as I have no experience using veriloga in cadence before.
Based on the error message, you are using the cell name "CNTfet".
In the veriloga code, did you change the module name to "CNTfet" ?
In reply to kristen:
Is the problem solved? I am facing the same problem. At the beginning I encountered a netlist error message. Now I somehow got rid of it.
Now it is showing this error -
Internal error found in spectre during hierarchy flattening, during circuit read-in.
FATAL(SPECTRE -18) : Segmentation fault
How do I get through this?
What is the model file that is to be selected from the model libraries in ADE? Are there any other changes to be made in the ADE before running this?
Please help. Thanks.