Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I am new to Cadence forums so please forgive me if I am in the wrong forum ( and please tell me the correct one also!! )
My query is that I am using Cadence Modelwriter for making an ADC (using veriloga). I am just not sure about the definitions which have been generated by the code. As a result i am not able to correctly parametrize the ADC for the required specifications.
I would like to know what is "tconv", and "slack" in the code. I am trying to build a 3-bit ADC and the input clock frequency should be 2.5 GHz and more.
Without seeing the actual VerilogA produced by the Modelwriter it is difficult to comment, and I haven't got the time to run it to see what it might produce. Aren't the parameters documented in the produced code? However, I would think that 'tconv' would be the time taken for the conversion from Analogue to Digital. Actually, never mind, I typed "tconv slack ADC" into a Google search box, and lo and behold I found this in the first few results returned:
// slack = The smallest time interval considered negligible for
// cross event on clock [S]
// tconv = Delay from threshold crossing to output change [S]
I was right on both counts. By the way, you are in the correct forum for this sort of question. Hope this helps you.
In reply to skillUser:
Thanks for your reply. I have a couple of questions. (fyi...the code is pasted below)
1. what sort of an adc is the code generating? Does it require a ramp input because when I am passing an analog signal i am just not getting any results?
2. could you approximately give me an idea how to calculate the conversion time for a signal of input say, 3 GHz or more?
// FUNCTION: Analog to Digital Converter// VERSION: $Revision: 2.13 $// AUTHOR: Cadence Design Systems, Inc.//// GENERATED BY: Cadence Modelwriter 2.31// ON: Tue Oct 30 17:09:28 CET 2012//// Description: Ideal Analog to Digital Converter// Generates an N bit ADC.// - selectable logic output levels// - model valid for negative values of vmin// - adjustable conversion time, and rise/fall time// This model is an example, provided "as is" without express or// implied warranty and with no claim as to its suitability for// any purpose.//// CCR 563324 changed voltage to electrical//// PARAMETERS:// slack = The smallest time interval considered negligible for// cross event on clock [S]// tconv = Delay from threshold crossing to output change [S]// trise = Rise time for digital output signals [S]// trise = Rise time for digital output signals [S]// vmax = ADC Full scale output voltage [V]// vmin = ADC Zero scale output voltage [V]// vone = The voltage of a logical 1 on digital outputs [V]// vth = Threshold value of clock signal [V]// vzero = The voltage of a logical 0 on digital outputs [V]//`include "discipline.h"`include "constants.h"`define NUM_ADC_BITS 3module a2d_ideal (vin, clk, dout); input vin, clk; electrical vin, clk; output [`NUM_ADC_BITS-1:0] dout; electrical [`NUM_ADC_BITS-1:0] dout; parameter real vmax = 1.2; parameter real vmin = 0; parameter real one = 1.2; parameter real zero = 0.0;
parameter real vth = 0.7; parameter real slack = 10.0p from (0:inf); parameter real trise = 0.001n from (0:inf); parameter real tfall = 0.001n from (0:inf); parameter real tconv = 0.5n from [0:inf); parameter integer traceflag = 0; real sample, vref, lsb, voffset; real vd[0:`NUM_ADC_BITS-1]; integer ii, binvalue; analog begin @(initial_step or initial_step("dc", "ac", "tran", "xf")) begin vref = (vmax - vmin) / 2.0; lsb = (vmax - vmin) / (1 << `NUM_ADC_BITS) ; voffset = vmin; if (traceflag) $display("%M ADC range ( %g v ) / %d bits = lsb %g volts.\n", vmax - vmin, `NUM_ADC_BITS, lsb ); generate i ( `NUM_ADC_BITS-1, 0) begin vd[i] = 0 ; end end @(cross ( V(clk)-vth, 1, slack, clk.potential.abstol)) begin binvalue = 0; sample = V(vin) - voffset; for ( ii = `NUM_ADC_BITS -1 ; ii>=0 ; ii = ii -1 ) begin vd[ii] = 0; if (sample > vref ) begin vd[ii] = one; sample = sample - vref; binvalue = binvalue + ( 1 << ii ); end else begin vd[ii] = zero; end sample = sample * 2.0; end if (traceflag) $strobe("%M at %g sec. digital out: %d vin: %g (d2a: %g)\n", $abstime, binvalue, V(vin), (binvalue*lsb)+voffset); end generate i ( `NUM_ADC_BITS-1, 0) begin V(dout[i]) <+ transition ( vd[i] , tconv, trise, tfall ); end endendmodule`undef NUM_ADC_BITS