Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
We have a problem in 5.1 layout or layout XL that some of the pins we put in our layout (at the top level of a large design) do not show visible names when we instance the cell at the next level up and hide the insides (using ^f), even after turning on the editor display options "instance pins" and "pin names". It is important to us to have visible pin names to make the cell easier to use by other parties. Some of the pins do show names, but others do not. These pins that do not show their names were not created with pin name labels, but they do have labels on the same layer as the pin and the label origin is inside the pin rectangle. Even using Edit/Other/Attach.. to attach the label to the pin rectangle does not make the name show up at the next level up. The label is on the same layer (with layer, e.g. M4 and purpose "lbl") that the pin rectangle has. What is going on here and is there anything we can do about it? Do we have to recreate all the pins using the option to attach a label to the pin at the time of pin creation?
Thanks for any tips. We could find nothing about this by web search.
This is using Cadence custom IC version 5.10.41, in particular I get
If things are displayed at level 0 (i.e. the insides hidden), pin labels only show up if they are "textDisplay" objects. Conventional labels don't show up - even if attached to the pin. textDisplay objects are special labels which automatically show the value of a database attribute or property - so they stay in sync with the terminal name, say.
Unfortunately there isn't (and I was slightly surprised by this) a built-in menu to create a textDisplay. You can use the SKILL function dbCreateTextDisplay to do this though.
In reply to Andrew Beckett:
Thanks for this informative response Andrew. A SKILL expert could create such a function to take a selected pin and add a visible text display to it that could then be manipulated, e.g. sized, aligned etc. But since the dbCreateTextDisplay requires a lot of inputs including object, owner, etc, that presumably can be extracted from a selected pin object if one knew SKILL a bit better (which we do not) it seems that for us the best solution is just to recreate the pins using Create/Pin and choosing a text display label at time of creation.