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Hi, I'm trying to design a simple decoder in which I'm using my own and and invertors with my own VDD and GND.
I created the VDD and GND pins in the invertor, nand. and to form and I used nand and invertor. I have also created extrarnal pins for VDD and GND for and symbol as well.
Now when I try to simulate it by connected all the gates to VDD and GND, I'm not able to get the result. I'm getting the following error.
ERROR (OSSHNL-249): There is no corresponding terminal for 'GND' (on placed master 'myand3/symbol') in
switch master 'myand3/cmos_sch'. Netlisting will continue if this terminal can be
ignored. Otherwise, ensure that you have a corresponding terminal in switch
master and netlist again.
ERROR (OSSHNL-249): There is no corresponding terminal for 'VDD' (on placed master 'myand3/symbol') in
Netlist Error: An invalid terminal list has been encountered. Use the Convert
Artist Bulk Nodes utility through the Tools - Conversion
Tool Box menu on the CIW. cell-view "NCSU_Digital_Parts" "pfet" "spectre"
Tool Box menu on the CIW. cell-view "NCSU_Digital_Parts" "nfet" "spectre"
End netlisting Nov 24 15:22:39 2012
ERROR (OSSHNL-514): Netlisting failed due to errors reported before. Netlist may be corrupt or may not be produced at all. Fix reported errors and netlist again.
Any help will be most appreciated.
The error message suggests that you have a difference between the pins on the cmos_sch and symbol views of your myand3. You didn't mention myand3, so not sure what you've done! Perhaps some pictures might help of the myand3 schematic and symbol if you can't work it out? (use the Options tab to attach a picture - you'll probably have to do two appends to get both pictures). In IC61 you can do File->Export Image to save a picture...