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How can I set min. num. of cuts, wire width per metal, use of square collinear vias and other options for geometric wire without starting VXL, making my own contraint and setting it for default.
I assume that the geometric wire has the same properties (or most of them) as the "real" wire.
Is this a bug or a feature? Since in Virtuoso L there is no Wire Asissitant to set all these options (IC6.1.5 ISR13).
It's not a bug. You can create the constraint group in the technology library (maybe as an incremental technology database if you don't want to write to your PDK), either by hand, or using VLS XL to create the constraint groups. Then you can pick the constraint group when using VLS L.
However, the power comes from using VLS XL. Is there a reason you don't want to use XL?
In reply to Andrew Beckett:
It's important when there is no VLS XL license, so only VLS L license is available.
I understood your first suggestion as :
1. Dump extisting tech to .tf file
2. Edit needed sections
3. Load edited .tf file (-> merge or replace, I assume both options are executed in the virtual mem so PDK stays intact? )
In reply to sPoK:
I would suggest using an incremental technology database. What that means is rather than attaching your design library to the technology library, use the reference option instead. This means that you have a technology file in your design library, but one that is mostly blank and will inherit from the technology library.
You can then set up your coinstraint group (either by editing the dumped ASCII tech file from your library, modifying, and re-loading, and then saving the tech file), or by using the Process Rule Editor in the constraint manager in VLS XL.