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I need to think of ways to generate top level circuit schematics using skill. I thought about using verilogIn, but I later realized that it does not provide me with much flexibility, and it does not allow me to map specific libraries to specific module/cell instances. What also happens is that I have symbols form different libraries with different pin lists that has the same module/cell names.
So as I looked through the sch* functions in skill, I was unable to identify a straightforward method to instance a symbol in a schematic, and specify labeled wires to be connected its pins. It doesn't have to be routed. I suppose one can go about opening each symbol to obtain its pin locations/labels, but it seems a bit tedious and prone to bugs. Does anyone know of any higher level functions to do this?
Hi TjaartHow about simply querying each symbol to get the terminal/pin info?symbolID~>master~>terminals~>nameHope that I am not misunderstanding your question. Or are you looking for schSymbolToPinList function?schSymbolToPinList("myLib" "myCell" "symbol")Best regardsQuek