I am having a problem with transistors nMOS model N_BPW_12_LLNVT in 65 nm UMC.
These transistors are triple-well. This is the first time I am using them and although my layout passes the DRC rules andthe LVS, when I simulate it in post-layout level, the DC voltages of my circuit goes to values different than the ones obtainedin schematic level. I suppose I am connecting wrong any of the wells of the transistor.
Has anyone used this kind of transistors or any triple well technology? I would like to know how I have to bias it.I want to used the bulk as an input.
Thanks in advance.
Hi ingenier7I think it might be better for you to contact UMC foundry support for this question. : ) They should be able to provide a good answer.Best regardsQuek