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I started with a vhdl behavioral filter design, did structural synthesis using Cadence BuildGates, place and route with soc encounter, imported output of encounter to virtuoso and extracted spice netlist using divaEXT.rul. My experimentation is supposed to be on the spice netlist.
The problem is I need to insert sensors in the filter design and connect them to certain modules. I have a transistor level implementation of filter (it cannot be represented as a gate level design). I was confused where to insert it in the flow so I specified those certain modules as partitions in soc encounter expecting a final structural netlist where I thought I could insert the sensors. But it is not working.
Can you suggest me another way to insert my filters in the flow?
Thanks a lot,
Hi ShinyIt sounds like you are exploring a mixed-signal design flow. How about this?a. Create abstract views for the sensors using abstract generatorb. Export LEF files from the abstract viewsc. Use the LEF files in your Encounter flow together with the other LEF files Best regardsQuek