Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I would like to measure delay on signal "gap" simulated on two temp -40 and 125 with "trigger" option like:
dly_fr=delay( v("gap") 0.75 1 "falling" v("gap") 0.75 2 "rising" 1 1 t "trigger")
I am getting results like:
time delay(v("gap" delay(v("gap"
temp -40 125
17.8748u 38.4359u 7.67508u
56.3107u 9.60973u 38.4348u
65.9204u 38.4462u 9.60979u
104.367u 9.60927u 38.4452u
but I am expecting results something like:
17.8748u 38.4359u 38.XXXXu
56.3107u 38.XXXXu 38.4348u
65.9204u 38.4462u 38.XXXXu
(bold are expected values which also could be measured manually)
Signal shape is:
___ ___ ___ ___
___| |___| |_____________| |___| |________ < fr >
and I would like to measure value fr.
How can I correctly measure value fr? What caracters 1 1 t in the command line (marked bold) mean?
Which subversion are you using? In recent versions that I've tried, ViVA uses the newer keyword argument form of delay() which is much clearer to see what the arguments mean because they are passed by name rather than order.
The subversion can be found by doing Help->About... in the CIW.
In reply to Andrew Beckett:
I am using version IC6.1.5-64b.500.10
In reply to jerry124:
If you build the expression in that version (using the calculator) you'd get the newer keyword argument version of the function - for example:
delay(?wf1 v("gap" ?result "tran"), ?value1 0.75, ?edge1 "falling", ?nth1 1, ?td1 0.0, ?wf2 v("gap" ?result "tran"), ?value2 0.75, ?edge2 "rising", ?nth2 2, ?td2 0.0 , ?stop nil, ?multiple nil)
which is much clearer as every argument is named. I did a bit of digging, and the ordered arguments are in this order (we seem to have removed this from the documentation):
wf1 value1 nth1 edge1 wf2 value2 nth2 edge2 period1 period2 multiple xName
The default is that the second edge is relative to time, rather than the first edge.
So I believe your expression is equivalent to:
delay(?wf1 v("gap" ?result "tran"), ?value1 0.75, ?edge1 "falling", ?nth1 1, ?td1 0.0, ?wf2 v("gap" ?result "tran"), ?value2 0.75, ?edge2 "rising", ?nth2 2, ?td2r0 0.0 , ?stop nil, ?period1 1 ?period2 1 ?multiple t ?xName "trigger" )
This means that:
It's not clear to me if you really want the ?multiple occurrences or not.
So my recommendation would be to try building the expression in the calculator and check to see what you're getting, rather than using this positional argument version (I even checked back in IC5141 and the keyword argument version is documented there too).