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However, one more thing must be done when people copy it to make their own arbitrary bus sizes: rename the module within the veriloga code!
For example, a 16 bit bus would need:
module busset8(outbus); -> module busset16(outbus);
Also, a question about these bussets. Can the setval parameter be changed at some point in time during a transient simulation? If so, what are the various options for doing so and which do you recommend?
You are right - I guess I assumed that copying and renaming the cell (hopefully to a library under your own control!) went without saying, but I should have included that step.Regarding whether (or how) you would change the setval during simulation, I can not think of how you would be able to do that with the cell as it is. Of course, you could use a couple of them, set to different values, and then analog switches to toggle between, but that's a bit messy. I think ideally a knowledgable Veriloga writer (which I am not) would probably be better off building a version of this cell that takes a voltage input as the "setval" parameter. Then, a vpwl or vpulse could be used to dynamically change the setval property. - Hugh
Yes, I have done the messy method, but am looking for a cleaner solution. :-)
Alas, I am not very experienced with Veriloga either (usually I know just enough to get by on), so I am hoping someone might help us. Hint, hint...
Somehow, I was under the impression that the bit assignment was only performed at the beginning of a simulation due to the use of the 'generate' command. Thus, adding another input to be driven by a source would not help. Anyone know more about this?
Actually, I am not thinking very clearly here - what you are really looking for is simply an ideal DAC. There already exists such an animal in the bms library, called dac_BiOB_8. If you set up the reference voltage correctly, then you can just feed this an analog input voltage and get whatever digital output you want. (For this particular DAC you will also need to feed it a clock signal each time you change the value.)It appears that this, too, could be copied (to a different name!) and scaled to a different bus size by changing the internal SIZE parameter (plus pin names, etc., and maybe also the internal note that talks about number of states, just to be consistent). I have not tried it though, so no guarantees!- Hugh
OOPS! What I meant to say was, an ideal ADC - not a DAC! There is one of those too in bmslib - called adc_BiOB_8. And the parameter you would change appears to be the HIBIT parameter.Sorry for any confusion.- Hugh
Yes, I had briefly looked at that, but I disliked adding yet another clock signal just to trigger the change in value. It is cleaner than the 2 bussets + switch, though.
I just wish veriloga had the same type of regular event control that verilog has, not just the analog event controls. Then a simple always @(setval) would cause the change in value. But I'm not going to switch to spectreVerilog just to get that.
Sure seems like there should be a cleaner way...
Its relatively easy to add a clock signal (or a period parameter) and make that block a "counter", or two make it switch between 2, 3 or a fixed set of numbers.. since parameters are "fixed" for a given simulation, you would have to add an input pin. VERILOG has a nice feature called "tasks" so in the ams version you can create and activate tasks in your tcl script to set the value to an arbitrary value.. but this doesn't work in spectre.. HOWEVER you can pass its variable from an Artist Design Variable, so that you can do a DC or AC (or parametric ) sweep of that variable - THAT was the reason I create the first version of that, and I found I was recreating it for successive customers.. finally we got a chance to create the bmslib, and make it available to everyone.. So I'm quite glad to hear you find it useful.Here is an RF analysis compatible version of busset4 that counts..
// jbdavid`include "constants.vams"`include "discipline.vams"`define MAXBIT 3/======(*instrument module*)module busset4 (outbus)output [`MAXBIT:0] outbus;electrical [`MAXBIT:0] outbus;parameter integer setval = 0 from [0:(1<parameter real vhigh = 1.5parameter real vlow = 0;parameter integer countdir = 0 from [-1:1]; //down, dont count, upparameter real startcounting = 5n;parameter real period = 5n;parameter real trf = 10p;integer outval;analog beginif (analysis("tran")) begin@(initial_step) beginoutval = setval; end@timer(startcounting,period) if (countdir) beginoutval = (outval+countdir)%(1<endgenerate j (`MAXBIT, 0) beginV(outbus[j]) < endend else beginoutval = 0; // this is required to work with RF simsgenerate j (`MAXBIT, 0) beginV(outbus[j]) < endendendendmodule`UNDEF MAXBIT
the instrument module line SB(* instrument_module *)jbd