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I managed to get Encounter auto-route and place the design, imported it into the Virtuoso environment as a Layout view, then runned DRC, then runned LVS versus the CDL file of standard cells and verilog file exported from encounter.
Now, I want to put this layout inside another custom layed out design. Right now, I have one design with some transistors, manually connected in schematic, and manually layed out, so I want to add this layout to that design and put it in a top level block, and then DRC and LVS it.
The way I do manual designs is, I first do schematics by hand in SchematicsXL, then I export the CDL netlist, then I pass it through the LVS script of IBM kit to convert it to LVS suitable format. Then I do layout, and do LVS versus the CDL netlist.
But in this case, I am going to use the layed out and separately LVS'ed Layout I have in another cell. That another cell has only Layout view, and a Symbol view I created for it.
The thing is, once I put that symbol inside a schematic with custom elements, and try to export netlist, the system complains saying that there is no "schematic" view.
In my export window of netlist as a View List there is: auCdl schematic, and as stop view: auCdl.
My question is: How do I integrate my imported Layout block on a schematics level in my top level block with manually designed stuff around it? Because, there is no "schematic" view in that Layout block, I did its LVS versus the CDL file of standard cells lib and verilog file from encounter.
I searched and know that people also do something like, import verilog to schematics. But then, my another question is, can I avoid that step? I really do not want to deal with schematics, even though this design is not that big, but I dont want to deal with it during the next very big designs.
Is there a way to export netlist from schematics with symbol of another imported block which only has Layout view without dealing with its schematics?
Often people do Verilog-In the verilog to produce schematics, but another approach would be to create a copy of the symbol and make it the "auCdl" view, and set up the CDF so that it netlists the auCdl view as an instance of the block (you can specify the termOrder for auCdl in the CDF, which you could probably just auto-create by opening the symbol and running artGenerateHierSymbolCDF(geGetEditCellView()) ).
Then in Assura you can specify a mixture of CDL and Verilog netlists to LVS against. Note, I've not tried this personally for some time, but I think it should work OK.
In reply to Andrew Beckett:
In reply to Kabal:
exported CDL netlist with two modifications, *.RESI and the whole pin connection modification, which works for LVS, but which I think totally wrong to do it that way.
So, any ideas?
Note that the port order is not used for auCdl netlisting; it uses the termOrder in the CDF.
This has been spun off into a separate discussion, so won't repeat it here.