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I am using spectre as simulation tool , my design have 32 bit input pins how i can assign this bits with values
I use vector file but it works fine with single bit , when i increase radix more than 1 it fails
I use sitimulis file but it also fails
what is the most effective way to test 32 bit input pins in spectre
You didn't give enough information for anyone to help you. Please read the forum guidelines.
In reply to Andrew Beckett:
This my vector file
; enable generation of expected output vectors and comparison result waveforms.;output_wf 1; radix specifies the number of bit of the vector.radix 2 2; io defines the vector as an input or output vector.io i i ; vname assigns the name to the vector.vname A[[1:0]] B[[1:0]]; tunit sets the time unit.tunit ns; trise specifies the rise time of each input vector.trise 0.01; tfall specifies the fall time of each input vector.tfall 0.01; vih specifies the logic high voltage of each input vector.vih 1.1; vil specifies the logic low voltage of each input vectorvil 0.0; voh specifies the logic high voltage of each output vectorvoh 1.1; vol specifies the logic low voltage of each output vectorvol 0.50 3 3
10 1 1
this is the error
Only one connection to the following 4 nodes: A0 A1 B0 B1 No DC path from node `A<0>' to ground, Gmin installed to provide path. No DC path from node `B<0>' to ground, Gmin installed to provide path. No DC path from node `A<1>' to ground, Gmin installed to provide path. No DC path from node `B<1>' to ground, Gmin installed to provide path.
In reply to ahmed osama:
In my case if I used your vector file, I got:
Notice from spectre during topology check. Only one connection to the following 4 nodes: A A B B
That's because it generates signals A, A, B, B - and these weren't connected in my circuit. If you want A<1> etc, you'd use:
vname A<[1:0]> B<[1:0]>
If you want them called A1, A0, etc, you'd use:
vname A[1:0] B[1:0]
You're getting messages about other nodes - so it suggests that you've not got the names right in the vname statement.
this is how it supposed to be
It might help if you provided your actual vector file - given that the one you posted doesn't look like either of the graphs you have shown (it only had two time points in, neither of which matches the waves you've shown). The most likely reason is that you've got the vector file wrong - but without seeing it it's impossible to tell!
; enable generation of expected output vectors and comparison result waveforms.;output_wf 1; radix specifies the number of bit of the vector.radix 2 2; io defines the vector as an input or output vector.io i i ; vname assigns the name to the vector.vname A<[1:0]> B<[1:0]>
; tunit sets the time unit.tunit ns; trise specifies the rise time of each input vector.trise 0.01; tfall specifies the fall time of each input vector.tfall 0.01; vih specifies the logic high voltage of each input vector.vih 1.1; vil specifies the logic low voltage of each input vectorvil 0.0; voh specifies the logic high voltage of each output vectorvoh 1.1; vol specifies the logic low voltage of each output vectorvol 0.50 3 3
this is the vector file i use
I have no idea what you're doing wrong, but it cannot be reading that vector file to produce the graphs you show above (either the one you say you are getting, or the expected one). I ran this simple netlist:
//vec_include "forum.vec"tran tran stop=100n method=gear2only
I get the waveforms below.
when i run the vector file it gives me the expected signals (stimulis) but when i see the output signal only one signal is acting as excepted but the other signals are acting wrong .
Is their any solution you suggest , or can you suggest another solution for forcing this sitmuils (32 bit) (A<0> ,..... A<31>)
That would rather suggest that your circuit is not working properly. If the input signals are the right shape but the outputs are not what you expect, I don't see how giving the stimulus in a different way is going to magically make the circuit start behaving?
The vector file approach should be fine. That said, none of your graphs matched the example vector files you gave, so I really don't know if this is user error or circuit error. It certainly does not appear to be an issue with the tools.