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Actually i crated a Memristor Model by using VerilogA code. Then i designed logic gates by using the same with different methodology and i got correct simulated output but when i combined all individual logic gates to make a simple 1 bit adder then i got convergence error. I did simulation for 40n sec but i am getting result upto 6-8 ns . Even i am not able to see input pulse. Please help me to short out this problem. Iam attaching my schematic and log file
Transient Analysis `tran': time = (0 s -> 40 ns)
Trying `homotopy = gmin' for initial conditions.
Trying `homotopy = source' for initial conditions.
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 40 ns
step = 40 ps
maxstep = 800 ps
ic = all
skipdc = no
reltol = 1e-03
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = moderate
method = traponly
lteratio = 3.5
relref = sigglobal
cmin = 0 F
gmin = 1 pS
Warning from spectre at time = 38.8734 ps during transient analysis `tran'.
WARNING (SPECTRE-16266): Error requirements were not satisfied because of convergence difficulties.
Warning from spectre at time = 46.4423 ps during transient analysis `tran'.
tran: time = 1.245 ns (3.11 %), step = 308.4 ps (771 m%)
tran: time = 3.06 ns (7.65 %), step = 93.55 ps (234 m%)
Warning from spectre at time = 3.10126 ns during transient analysis `tran'.
tran: time = 5.205 ns (13 %), step = 205.2 ps (513 m%)
Warning from spectre at time = 6.0115 ns during transient analysis `tran'.
Warning from spectre at time = 6.1008 ns during transient analysis `tran'.
Further occurrences of this warning will be suppressed.
tran: time = 7.109 ns (17.8 %), step = 204.3 ps (511 m%)
Error found by spectre at time = 8.03662 ns during transient analysis `tran'.
ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified. Last acceptable solution computed at 8.03662 ns.
The values for those nodes that did not converge on the last Newton iteration are given below. The manner in which the convergence criteria were not satisfied is also given.
Failed test: | Value | > RelTol*Ref + AbsTol
Top 10 Solution too large Convergence failure:
I(I9.R2:1) = 3.27345 uA, previously 3.28612 uA.
update too large: | -5.69514 uA | > 1.55317 uA + 1 pA
I(I9.I1:p_n_flow) = 3.27345 uA, previously 3.28612 uA.
I(I9.R1:1) = -6.63437 uA, previously -3.59126 uA.
update too large: | 5.63895 uA | > 1.55653 uA + 1 pA
I(I9.I0:p_n_flow) = -6.63437 uA, previously -3.59126 uA.
I(V3:p) = -508.065 uA, previously -508.099 uA.
update too large: | 5.69437 uA | > 2.05796 uA + 1 pA
Top 10 Residue too large Convergence failure:
residue too large: | 575.245 mV | > 5.45743 mV + 1 uV
The following set of suggestions might help you avoid convergence difficulties.
1. Evaluate and resolve any notice, warning, or error messages.
2. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
3. Small floating resistors connected to high impedance nodes might cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
4. Ensure that a complete set of parasitic capacitors is used on nonlinear devices to avoid jumps in the solution waveforms. On MOS models, specify nonzero source and drain areas.
5. Perform sanity check on the parameter values using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings. Print the minimum and maximum parameter value using the `info' analysis. Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.
6. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.
7. Enable diagnostic messages by setting option `diagnose=yes'.
8. Use the `cmin' parameter to install a small capacitor from every node in the circuit to ground. This usually eliminates any jumps in the solution.
9. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.
10. Try to simplify the nonlinear component models in order to avoid regions in the model that might contribute to convergence problems.
Analysis `tran' was terminated prematurely due to an error.
finalTimeOP: writing operating point information to rawfile.
Trying `homotopy = gmin'.
Trying `homotopy = source'.
modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile.
Hi SameerFor convergence issues, I think it would be good if you can test if the problem still occurs using the latest version of MMSIM package. By the way, I think you had not provided any info on the version of spectre which you are using.terminal>spectre -WBest regardsQuek
In reply to Quek:
Thanks for your response. Here i am udating complete log file detail in which all information available viz verion etc.. I got from googling they was telling about to change the value of Cmin but from where i will get this option..........Also some block told about to change integration methode to gear or euler but i am not getting thesse option. Shall i change value of RELTOL ABSTOL or other parameter..
Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 10.1.0.204 32bit -- 14 Sep 2010
Copyright (C) 1989-2010 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.
Protected by U.S. Patents:
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Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.
User: root Host: cadence614 HostID: A0F02 PID: 14634
Memory available: 58.9127 MB physical: 820.8261 MB
CPU Type: Intel(R) Pentium(R) CPU P6100 @ 2.00GHz
Processor PhysicalID CoreID Frequency
Simulating `input.scs' on cadence614 at 11:40:37 PM, Sat Apr 19, 2014 (process id: 14634).
/Cadence/MMSIM10.1/tools.lnx86/spectre/bin/32bit/spectre input.scs \
+escchars +log ../psf/spectre.out +inter=mpsc \
+mpssession=spectre8_2568_46 -format sst2 -raw ../psf \
+lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 14634
Loading /Cadence/MMSIM10.1/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /Cadence/MMSIM10.1/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /Cadence/MMSIM10.1/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /Cadence/MMSIM10.1/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Time for NDB Parsing: CPU = 1.59876 s, elapsed = 2.67938 s.
Time accumulated: CPU = 1.59876 s, elapsed = 2.67938 s.
Peak resident memory used = 37 Mbytes.
Time for Elaboration: CPU = 369.944 ms, elapsed = 387.481 ms.
Time accumulated: CPU = 1.9687 s, elapsed = 3.07253 s.
Peak resident memory used = 57 Mbytes.
Time for EDB Visiting: CPU = 5.999 ms, elapsed = 7.19118 ms.
Time accumulated: CPU = 1.9747 s, elapsed = 3.08798 s.
Peak resident memory used = 57.3 Mbytes.
Notice from spectre during topology check.
Only one connection to the following 2 nodes:
Time for parsing: CPU = 14.998 ms, elapsed = 123.726 ms.
Time accumulated: CPU = 1.9897 s, elapsed = 3.21214 s.
Peak resident memory used = 58 Mbytes.
Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre8_2568_46, ).
In reply to SAMEERGARG:
Hi SameerYou are currently using spectre 10.1 which is already very out-dated. I think the current spectre 13.1 might resolve the convergence problem.Best regardsQuek
It's far more likely that the convergence issue is caused by your veriloga model or the connectivity of the circuit than it is by the version of the simulator you are using. I doubt changing to MMSIM 13.1 would solve this unless you got lucky. So please post your input.scs (so we can see the entire circuit) plus your memristor veriloga model.
Hii Quek & Andrew
Thanks for your responce. As per your guidline i simulate my libreries on updated version spectre13.1 and i got exactley what i want (Correct Output). But when i tried to resimulate then again same convergence error came in log window. I restarted my cadance 2-3 times then it worked again and later again same problem....Shall i change parameters what i discussed in privious post........
As I explained before, the major cause of convergence problems is the quality of the models. VerilogA gives you the freedom to do things which make it very difficult for a simulator to converge - you might get lucky with a poor model, but equally you might not. Altering accuracy parameters to reach convergence should not be your first step - it should be to check whether the models are realistic. Without seeing the example I would be reluctant to suggest altering reltol etc. For such a simple circuit I really would not expect convergence challenges unless something was wrong with the models or the circuit connectivity (eg inside the gates).
So please post the information I requested in my last post.
In reply to Andrew Beckett:
Thanks for your kind response. I am attaching simulation directory and current library in which my all logic blocs are available. I exactley dont know where i will get input.scs ile so i hope that it should be inside one of those folder...
Hiii Andrew Sir
Hearty Thanks for your intrest. I got that what u exactley told for input.scs. Please suggest me what kind of parameter i have to changed to avoid this error. from two days onward i could not do my further analysis so please guide me.....1 more think I would like to share... later i checked on Spectre 11.** version in which i got output frequentley so shall i asked for updated version or by changind some parameter can solve the problem
Hi SameerI am a little confused about the following comment which you had made:>>> As per your guidline i simulate my libreries on updated version
spectre13.1 and i got exactley what i want (Correct Output). But when i
tried to resimulate then again same convergence error came in log
window.Would you please confirm if you meant the following?a. Execute "Simulation->Netlist and Run"b. Successfulc. Without changing any setting, simply execute "Simulation->Netlist and Run" againd. Now it failsBest regardsQuek
I took a look at the testcase and models, and realistically it's more complex than I really have time to debug. Running "spectre +aps -ahdllint input.scs" does flag a few things that could be improved - but I think the right thing to do would be to follow this up with customer support (I'm travelling for a couple of weeks so have limited bandwidth for detailed debugging).
Thanks for your responce. Finally I got a solution of this convergence proble. What i did was i changed rise and fall time from pico to femto ,input pulse width from nano to Pico and at the same time incresed input DC voltage by 1 volt ie 5V now .... By doing so finally i got output...In my openion the default switching between ON to OFF state is very fast for current simulator integrating methode thats why it was not able to catch the adjact output. It is a logical answer dont know wheather it is correct or not???????????Well is there any side effect of these changes on performane of a system??????
I have one doubt. CMOS inverter has max break down voltage upto 7.2 volt that after this it is not giving proper output and during simulation it is giving convergence error. In my work my input voltage is minimum 8V due to some conditions.
So please tell me some mechanism by changing dimension or else so that i can use inverter upto 8V. Tell me some other alternative if available which i can use to make NOT gate. Please reply....