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I am using Calibre PEX to extract netlist for post layout simulation. The output format is spectre.
The way I am following is that firstly complete a schematic simulation, then take this simulation as a reference and just need to swap the netlist to the extracted netlist, then perform the layout simulation.
But there are something weird that when I changed the output node capacitor from 0.1fF to 1uF, the simulation results are almost the same.
The circuit is an OR gate, the Z port is output. Here are part of the netlist
subckt PM_TDC_or_test\%Z ( 1 2 7 )c0 ( 7 gnd! ) capacitor c=105453fc1 ( 2 gnd! ) capacitor c=105453fr2 ( 2 7 ) resistor r=20.5902r3 ( 1 7 ) resistor r=9.05844ends PM_TDC_or_test\%Z
x_PM_TDC_or_test\%Z ( N_Z_M5_d N_Z_M2_d Z ) PM_TDC_or_test\%Z
simulator lang=spectreinclude "TDC_or_test.pex.netlist_case.pex"subckt TDC_or_test ( A B gnd! vdda! Z )//// Z Z// vdda! vdda!// gnd! gnd!// B B// A AXM0 ( N_3_M0_d N_A_M0_g N_gnd!_M0_s N_gnd!_M0_b ) NM_33 l=3.5e-07 w=5e-07 \ ad=1.05e-13 as=1.8e-13 pd=9.2e-07 ps=1.72e-06 nrd=0.42 nrs=0.72 sa=3.6e-07 \ sb=1.13e-06XM1 ( N_gnd!_M1_d N_B_M1_g N_3_M0_d N_gnd!_M0_b ) NM_33 l=3.5e-07 w=5e-07 \ ad=1.8e-13 as=1.05e-13 pd=1.72e-06 ps=9.2e-07 nrd=0.72 nrs=0.42 sa=1.13e-06 \ sb=3.6e-07XM2 ( N_Z_M2_d N_3_M2_g N_gnd!_M2_s N_gnd!_M0_b ) NM_33 l=3.5e-07 w=8.75e-07 \ //output nmos ad=3.15e-13 as=3.15e-13 pd=2.47e-06 ps=2.47e-06 nrd=0.411429 nrs=0.411429 \ sa=3.6e-07 sb=3.6e-07XM3 ( 6 N_A_M3_g N_vdda!_M3_s N_vdda!_M3_b ) PM_33 l=3.5e-07 w=1e-06 ad=2.1e-13 \ as=3.6e-13 pd=1.42e-06 ps=2.72e-06 sa=3.6e-07 sb=1.13e-06XM4 ( N_3_M4_d N_B_M4_g 6 N_vdda!_M3_b ) PM_33 l=3.5e-07 w=1e-06 ad=3.6e-13 \ as=2.1e-13 pd=2.72e-06 ps=1.42e-06 sa=1.13e-06 sb=3.6e-07XM5 ( N_Z_M5_d N_3_M5_g N_vdda!_M5_s N_vdda!_M3_b ) PM_33 l=3.5e-07 w=1.75e-06 \ //output pmos ad=6.3e-13 as=6.3e-13 pd=4.22e-06 ps=4.22e-06 sa=3.6e-07 sb=3.6e-07c_1 ( 6 gnd! ) capacitor c=0.0955951f//include "TDC_or_test.pex.netlist_case.TDC_or_test.pxi"//ends TDC_or_test
It seems that the "gnd!" node in .pex file is floating. So I changed the netlist to below, then it works fine. But in spectre a net ends with "!" means a global net, but why it can't be recognised? or something I missed?
Any reply will be appreciated!
subckt PM_TDC_or_test\%Z ( 1 2 7 gnd! )c0 ( 7 gnd! ) capacitor c=105453fc1 ( 2 gnd! ) capacitor c=105453fr2 ( 2 7 ) resistor r=20.5902r3 ( 1 7 ) resistor r=9.05844ends PM_TDC_or_test\%Z
x_PM_TDC_or_test\%Z ( N_Z_M5_d N_Z_M2_d Z gnd! ) PM_TDC_or_test\%Z
PS: I am using IC6.1 .5-64b
I know the reason. I need to add "global gnd!" in input.scs, as well as V5 (gnd! 0) vsource dc=0 type=dc, to declare gnd! to be ground.