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Hi,I have a question about assura (or LVS extractor in general), how can the tool determine if the pin is the "drain" or "source" of the transistor??Can I control that to get special output netlist (SPICE netlist)..??Thanks in advance,Ahmad
I'm not really an expert but I believe the tool doesn't really make a distinction between source & drain. It simply matches nets in the device and the connectivity takes care of itself. Now if you are talking about a simple layout cell you are making for your individual device then I would create & place pins on the sorce & drain and make the labels match the pin names from the symbol view.