Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
We used the method of print DC model parameters and found the mobility of PMOS-0.01528 A/V2 and NMOS-0.02118 A/V2, Which contradicts the basic fact the mobility of NMOS is greater than PMOS. We are using the standard Vt devices for TT corner case. Can you tell us what is the constant value of mobility for PMOS and NMOS and how to find them in model library.
First of all, by asking the question to me, you're rather excluding anyone else from answering. This is not "Andrew's forum" - it's a community forum which I happen to answer a fair number of questions in my spare time.
Secondly, you provided little information about exactly what you're looking at, or which technology you're using. At a wild guess, you're looking at u0 from the models and are using gpdk045. First of all, u0 is the "low field surface mobility at tnom" - it's not the effective overall mobility. If you look in the bsim4 equations in <MMSIMinstDir>/doc/spectremod/spectremod.pdf you'll see there are several complex equations describing how effective mobility (ueff) is computed. Of course, you might not be using this model if it's a different PDK you're talking about, but there will be similar equations for other models.
It's a slight anomaly that u0 in the nch models is lower than the pch models in gpdk045 (although I suspect you made a mistake in your post because you have the NMOS higher than the PMOS, which is what you'd expect - so my guess is you got the numbers back to front if you were looking at u0). However, in my quick simulations if I look at ueff (an output operating point parameter for bsim4) it's higher for NMOS than PMOS. Since numerous parameters make up the effective mobility, it may just be that u0 is a little unusual because of the fitting of this fictional process...
All I said above may be nonsense if you're not talking about gpdk045 or had the numbers the right way around in the first place.