Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I am migrating my pcells to IC6, and I am wrestling with the new via model. Our PDK uses "standard vias", so I understand that I need to use the dbCreateVia function.
Apparently, I can override paramaters, even for standard vias, so I can use the following syntax:
dbCreateVia(cvId viaId list(x y) list(list("cutRows" 2) list("cutColumns" 3)))
There is several unique stuff in creating via compare to other instances. As what i know, there is no pption to specify the justification if you using SKILL function -dbCreateVia to create via rather than the GUI.
Fortunately, the justification can be specific by doing some manual calculation and input the value as an option - "originOffset". The full syntax of dbCreateVia will be:
dbCreateVia( d_cvId d_viaDefId l_origin t_orientation l_paramlist)
eg: dbCreateVia( cvId vidDefId list(x y) "R0"
list( list("cutRows" 2) ;row
list("cutColumns" 4) ;column
list("cutSpacing" list(x y)) ; cut spacing for x and y
list("layer1Enc" list(x y)) ; enclosure for layer1
list("layer2Enc" list(x y)) ; enclosure for layer2
list("cutWidth" 0.2) ; cut width
list("cutHeight" 0.4) ;cut height
list("originOffset" list(x y))) ; justification
You can change the justification by changing the option -"originOffset". The input must be in l_point which specify the x and y offset from center of the via. A mathematic calculation is needed to measure the distance from the origin point to the center of the via.
In reply to kbhow:
Let's say, I wanted to specify the x-cutSpacing, but I did not know the y-cutSpacing, and I wanted to leave the y-cutSpacing at the default value.
How would I do this inside the pcell's SKILL environment? Surely, there is something more elegant than lxComputeViaParams. Does it even work in the pcell environment?
In reply to TrevorB:
Please create a service request at Cadence Customer Support. lx functions are not legal in pcells, so that's not an option; I'm not aware of a convenient way of doing this within a pcell, so it would be best to ask via customer support and then an enhancement request can be filed, and maybe R&D can come up with a workaround.
In reply to Andrew Beckett:
Thanks, Andrew! I filed a SR. Hopefully, R&D can come up with something.
Just wondering if you were able to come up with a solution to your problem? I would also like to write some skill code to convert one via type to another. But it seems like the only way possible in IC6 is to delete the old via and recreate a new one. But to create an identical via to the original, I would need to set the parameters such as justification.
In reply to Tsien:
I never found or was given a clean solution. I wrote some bimodal code to consistently place a contact in either IC5.1 or IC6.1, like below.
procedure(apcCreateContact(@key ;_Oct 7 11 tbowen 528
origin = 0:0
rotation = "R0"
params = append1(params list("cutRows" rows))
params = append1(params list("cutColumns" columns))
when(xPitch && yPitch && width && height
params = append1(params list("cutSpacing" list(xPitch-width yPitch-height)))
params = append1(params list("cutWidth" width))
params = append1(params list("cutHeight" height))
inst = dbCreateVia(cv master origin rotation params)
when((stringp(xBias) && rexMatchp("[lLrR][eEiI][fFgG][tThH]" xBias) && columns > 1) ||
(stringp(yBias) && rexMatchp("[lLuU][oOpP][wWpP][eE][rR]" yBias) && rows > 1)
xOffset = yOffset = 0.0
bBox = inst~>bBox
when(stringp(xBias) && !rexMatchp("[cC]enter" xBias) && columns > 1
xOffset = viaEdgeCenter - width(bBox)/2.0
xOffset = width(bBox)/2.0 - viaEdgeCenter
) ; ** cond rexMatchp **
) ; ** when xBias **
when(stringp(yBias) && !rexMatchp("[cC]enter" yBias) && rows > 1
yOffset = viaEdgeCenter - height(bBox)/2.0
yOffset = height(bBox)/2.0 - viaEdgeCenter
) ; ** cond rexMatchp **
) ; ** when yBias **
inst~>originOffset = xOffset:yOffset
fprintf(stdout "(E) apcCreateContact: Offset bias ignored, because viaEdgeCenter was not a number (xBias=%L, yBias=%L\n" xBias yBias)
) ; ** if numberp **
) ; ** when xBias **
inst = dbCreateInst(cv master nil origin rotation)
inst~>l = width
inst~>w = height
inst~>row = rows
inst~>column = columns
inst~>xPitch = xPitch
inst~>yPitch = yPitch
inst~>xBias = xBias
inst~>yBias = yBias
) ; ** if isOA **
) ; ** let **
) ; ** procedure apcCreateContact **
Yes, that definitely helps. Thanks for the reply.
Its too bad that cadence doesn't improve the via accessibility through SKILL in OA.