Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I know that people can observe some transistor parameter changes during the monte carlo simulation, but there is no options to let user choose width or length of a transistor as a observed parameter, what's your method?
by the way, my approach is to build an expression including some parameters picked up by "opt" in calculator, but the transistor size is not there.
generally, are all the transistors in a circuit applied the same variation in a simulation? or each transistor has its own variation in the simulation? I noticed that some people mentioned one model card and multiple model card, is this related to the transistor dimension variation?
You can access the size of the transistor using pv("/I7/M5" "w" ?result 'instance) (same for "l"). That's the parameter as define in the netlist. If you want the effective width and length, that would be pv("/I7/M5" "weff" ?result 'output) (and "leff" for length) The parameters that are output are in the Output Parameters section of "spectre -h bsim4" (or whatever model you're using). For example:
================= Output Parameters=================1 weff (m) Effective channel width (alias=lx62).2 leff (m) Effective channel length (alias=lx63).3 weffcv (m) Effective channel width for CV (alias=lx64).4 leffcv (m) Effective channel length for CV (alias=lx65).5 vfbsd (V) Flat band Voltage between the gate and Drain/source diffusions (alias=lx75).6 rgbi (Ohm) Gate bias-independent resistance.7 adeff (m^2) Effective drain area.8 aseff (m^2) Effective source area.9 pdeff (m) Effective drain perimeter.10 pseff (m) Effective source perimeter.
However, it's quite likely that your monte carlo models are not varying the weff/leff of the device, but instead varying the vt or some other parameter of the model. So you might not see anything nevertheless.
In reply to Andrew Beckett:
thanks so much!