Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm trying to write a procedure that will follow a signal down the hierarchy and return a list of instances which were traversed. I've been able to do this successfully, with the code below, as long as the path does not contain iterated instances. With iterated instances I'm struggling with how to map the signal name a one level to the name used at the next lower level.
My basic approach is as follows:
1) use dbFindSigByName to find the signal object assocaited with the desired signal at a given level of hierarchy.
2) from the signal object, use instTerms to determine which instance terminals the signal is connected to and at which index of that terminal the desired signal is located
3) for each instTerm, open the associated instance and use dbGetMemName to determine what name the original signal name was mapped to.
4) Repeat the whole procedure for the current instance with the mapped signal name until the desired stop cell is reached or it has descended into cell from a base cell library ("xxXxx"). At this point the instance path is printed out.
When descending into an iterated instance the mapping step with dbGetMemName fails since it doesn't account for the iterated intances. For example, consider cellview where 3 iterated instances I<0:2> have a net "upper<0:5>" connected to terminal "lower<0:1>". If I'm following the signal "upper<3>" down, I need to determine that "upper<3>" maps to "lower<1>" of instance I<1>. Are there any built-in functions to assist with this mapping or do I need to roll my own?
Any help would be greatly appreciated.
;; usage: traceSignal("signal<2>" "stopCellName")
procedure(traceSignal(sig_name stop_cell @optional (cv geGetEditCellView()) (sList '() ) (iList '("") ) (cList '() ) ) let( (net_l net net_d sig_d sig sig_l instTerm_l instTerm bit) if(sig_d = dbFindSigByName(cv sig_name) ;; get the signal object for the signal name then sList = cons(sig_name sList) ;; add signal name to hierarchical list foreach(instTerm_l sig_d~>memInstTerms instTerm = car(instTerm_l) ;; instance terminal to which signal connects bit = cadr(instTerm_l) ;; bit index of signal on instance terminal followDown(instTerm bit stop_cell sList iList cList) );foreach(instTerm else printf("Signal %s not found\n" sig_name) ); if(sig_d t );let);procedure(traceSignalprocedure(followDown(instTerm bit stop_cell sList iList cList) let((cv term_name inst_name inst_base_name inst_num cell_name lib_name sig_name) term_name = instTerm~>name inst_name = instTerm~>inst~>name cell_name = instTerm~>inst~>cellName lib_name = instTerm~>inst~>libName iList = cons( inst_name iList) ;; add instance name to hierarchical list cList = cons( cell_name cList) ;; add cell name to hierarchical list if(lib_name == "xxXxx" || cell_name == stop_cell then ;; don't descend any further printf("%s\n" buildString( reverse(sList) " -> " )) printf("%s\n" buildString( reverse(cList) " : " )) printf("%s\n" buildString( reverse(iList) "/" )) else getWarn() when(cv = dbOpenCellViewByType(lib_name cell_name "schematic" ) ;; descend hierarchy sig_name = dbGetMemName(term_name bit) ;; determine signal name at lower level traceSignal(sig_name stop_cell cv sList iList cList) ;; look for signal dbClose(cv) );when(cv ); if(lib_name);let);procedure(followDown
You'll hve to "roll your own", but this is all you really need:
; makes a list of lists of all instances and terminals of an iterated terminal.procedure( getInstAndTerm( memTerm) let( ( ( term car( memTerm)) ( index cadr( memTerm)) ( inst car( memTerm)->inst) instNameMembers termNameMembers instTermPairs )
instNameMembers = dbProduceMemName( inst->name) termNameMembers = dbProduceMemName( term->name) foreach( instMember instNameMembers foreach( termMember termNameMembers instTermPairs = tconc( instTermPairs list( instMember termMember)) ) )
nth( index car( instTermPairs)) ))
In your example:
sig = dbFindSigByName(geGetEditCellView() "upper<3>") db:0x2194a896mit = car(sig~>memInstTerms) (db:0x2194a912 3)Notice the bit number 3.it = getInstAndTerm(mit)("I<1>" "lower<1>")
So essentially, the inst term pairs are:0: I<0> lower<0>1: I<0> lower<1>2: I<1> lower<0>3: I<1> lower<1>4: I<2> lower<0>5: I<2> lower<1>
In reply to dmay: