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I created pcell using the code specified in rod objects in my install directory. To achieve it entered following code in my CIW and created pcells. My version is 6.1.
Pcell working fine without any errors. Then I created a schematic with all options(fingers, multipliers....) and get all devices in layout by doing Gen From source. When I overlap two pcells then it automatically adjusts side by side by merging drains and taps. Now I need control of that adjustments because I didn't get minspacing at drain/source merging.
Is there any command in techfile to specify instance to instance space when they are overlapped in VXL mode. Generally When we overlap two instances in VXL then it automatically adjusts the instances. But in my VXL while merging two instances it takes more space than minimum space.
In reply to Sarvani:
It's not a "techfile" function. If you have an abutFunction to control auto-abutment, the abutFunction can return the offset. Search for "abutFunction" in the documentation - there's an explanation of it there. In the sample pcell code, it's in components/mos/mos.il (function is called spcMosAbutFunction)
In reply to Andrew Beckett:
Thankyou very much. Now it works superbly. But I have a problem when running LVS. I have pcells spcnmos, spcpmos(layout,symbol,auLvs,ivpcell...) in library. I created one inverter(layout and schematic)by using that pcells. It oparates well in VXL mode. While doing LVS it shows following error.
1 0 ((L "Y")((1 "spcnmos" ( "D" "G" "S" "B"))(1 "spcpmos" ( "D" "G" "S" "B")))(S "Y")((1 "car" ( "D" "G" "S" "B"))(1 "car\" ( "D" "G" "S" "B"))))
SYNTAX ERROR found at line 1 column 129 of file *string*
In LVS extractfile.rul file I wrote this for device recognition, parameter extraction.
extractMOS( "spcnmos" spcnmos cpoly("G") ndiff("S" "D") psub("B") spiceModel( "spcnmos" ) flagMalformed cellView( "spcnmos ivpcell" ) ); end extractMOS l_NMOS = measureParameter( length ( spcnmos inside cpoly ) 0.5u ) w_NMOS = measureParameter( length ( spcnmos coincident cpoly ) 0.5u ) nameParameter( l_NMOS "l" ) nameParameter( w_NMOS "w" ) nameParameter( w_NMOS "effW" ); REQUIRED FOR SPECTRE /* 1v pmos */ extractMOS( "spcpmos" spcpmos cpoly("G") pdiff("S" "D") nwell("B") spiceModel( "spcpmos" ) flagMalformed cellView( "spcpmos ivpcell" ) ); end extractMOS l_PMOS = measureParameter( length ( spcpmos inside cpoly ) 0.5u ) w_PMOS = measureParameter( length ( spcpmos coincident cpoly ) 0.5u ) nameParameter( l_PMOS "l" ) nameParameter( w_PMOS "w" ) nameParameter( w_PMOS "effW" ); REQUIRED FOR SPECTRE
My LVS is not running perfectly. Actually in this technology we have only caliber rulefiles. So I wrote layer derivations, definitions, extract devices in extract.rul file. I got following warnings in LVS.wrn file. Please Solve this if you have Idea about verification codes.
This LVS is for INVERTER
Assura Errors & Warnings Search (PLEASE CAREFULLY REVIEW THESE MESSAGES)================================================================================WARNINGS & ERRORS found in Assura NVN Run Log file-------------------------------------------------------------------------------- WARNING (AVLVSNN-10050) : mosDevice - cell 'spcnmos' not found. WARNING (AVLVSNN-10050) : mosDevice - cell 'spcpmos' not found.*ERROR* Device 'car(BJT)' on Schematic is unbound to any Layout device.*ERROR* Device 'spcnmos(MOS)' on Layout is unbound to any Schematic device.*ERROR* Device 'spcpmos(MOS)' on Layout is unbound to any Schematic device.
Here spcnmos,spcpmos are pcells. In extract.rule file I defined layer defitions and derivations. For extraction of MOS is like this.
npod = geomAnd( nimp diff ) ntox = geomAndNot( npod nwelli )
spcnmos = geomAndNot( geomAnd( ntox poly ) capdmy )
ppod = geomAnd( pimp diff) ptox = geomAnd( ppod nwelli )
spcpmos = geomAnd(geomAndNot( geomAnd( ptox poly ) capdmy ) pm)
extractMOS( "spcnmos" spcnmos cpoly("G") ndiff("S" "D") psub("Sub") spiceModel( "spcnmos" ) flagMalformed cellView( "spcnmos ivpcell" ) ); end extractMOS l_NMOS = measureParameter( length ( spcnmos inside cpoly ) 0.5u ) w_NMOS = measureParameter( length ( spcnmos coincident cpoly ) 0.5u ) nameParameter( l_NMOS "l" ) nameParameter( w_NMOS "w" ) nameParameter( w_NMOS "effW" ); REQUIRED FOR SPECTRE extractMOS( "spcpmos" spcpmos cpoly("G") pdiff("S" "D") nwell("Sub") spiceModel( "spcpmos" ) flagMalformed cellView( "spcpmos ivpcell" ) ); end extractMOS l_PMOS = measureParameter( length ( spcpmos inside cpoly ) 0.5u ) w_PMOS = measureParameter( length ( spcpmos coincident cpoly ) 0.5u ) nameParameter( l_PMOS "l" ) nameParameter( w_PMOS "w" ) nameParameter( w_PMOS "effW" ); REQUIRED FOR SPECTRE
In compare rule:
I didn't edit parallelmerge, seriesmerge, compare checkings. After these I wrote Like this
schematic( genericDevice( emptySubckt ) mosDevice( "spcpmos" ( "D" "G" "S" "Sub" ) "w" "l" ) mosDevice( "spcnmos" ( "D" "G" "S" "Sub" ) "w" "l" ) ) layout( mosDevice( "spcpmos" ( "D" "G" "S" "Sub" ) "w" "l" ) mosDevice( "spcnmos" ( "D" "G" "S" "Sub" ) "w" "l" ) ) mergeParallel( "spcpmos" merge parallelMOS ) mergeParallel( "spcnmos" merge parallelMOS ) mergeSeries( "spcpmos" noMerge ) mergeSeries( "spcnmos" noMerge ) compareParameter( "spcpmos" compareMOS ) compareParameter( "spcnmos" compareMOS )) ;end avCompareRulesI got 4 nets and 4 devices errors for INVERTER. And parameters errors are not showing in errors report but in layout parameter are diferent from schematic.
Hi SarvaniWould you please start a new thread for your LVS issue? It would help all our forum readers in differentiating the various issues which you are having. : )ThanksQuek
In reply to Quek:
I got solution for LVS problem from Quek. And thank you once again Quek. And I have another doubt on pcell. I have different pcells with different options. Can I saw the code for constructing that pcells? If possible how.
I have no idea what you're asking. If these are pcells which you created yourself (e.g. from the sample pcells), then yes, you have the code. Or if you wrote them yourself. But if they are from a foundry PDK, almost certainly you can't see the code.
Your question is extremely unclear as to what the problem actually is, or what you're trying to do.
I mean code for pcells which are from foundary PDK. And is there any document in install directory which tells about construction of PDK
You won't be able to see the foundry's pcell code unless they choose to let you see it. You could always ask them...
For your second question,
My source link ID is expired. I didn't able to go with grace period also.. Is the documentation present in my install directory?
No, it's only on Cadence Online Support.
Thank you verymuch Andrew.