Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Is it possible to have a stretch handle enabled/visible to a condition, such as a layer visible?
Presumably, in the PCell you would only call the rodAssignHandleToParameter() function when the test condition is true, otherwise don't call it. Is this what you mean? The visibility of the stretch handles is controlled by the Options -> Display -> Stretch Handles item, or the associated .cdsenv variable
layout displayStretchHandles boolean t
I'm not sure that you can make handles individually visible, but you should be able to create or not create the stretch handle as indicated above.
Hope it helps.
In reply to skillUser:
In reply to Eduardas:
It's not a bug. Most likely you have the displayStretchHandles setting stored on either the cellView, the library, or technology library. When a design is opened, display and editor options are searched for in this order:
Wherever it finds it first, will set the property on the window. So if it has been set in any of the top three, the cdsenv will have no effect because something more specific has overridden it.
To check, in the layout window do File->Properties and go to the Property tab (or shift-Q to bring up the cellView properties for most people). If it's not there, go over the library in the library manager and do RMB-> properties. Look for a property called viewProps and if it's there, it will have an EXPAND button next to it. This will popup another form with potentially multiple viewTypes, but the one you'd be after is maskLayout. Click on the EXPAND button next to that, and you should see any saved display properties. If it's not in the library, do the same process on the technology library that you're attached to.
In reply to Andrew Beckett:
Thank you for quick reply. I checked all this and did not find any viewProps...
To re-check, I created new lib & cell and have .cdsenv loaded. All this fine.
Most probably it was setted somwhere else. E.g working lib or techfile.
At least I can see stretch handlers now,