Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm having very strange issue here. When I run a transient simulation, the PSF output file is named 'an1.tran' and I am not able to run any OCEAN script on it, nor to do any calculation with the Results Browser and the calculator.
It always return me the same error message in the ICW :
expression evaluation failed: val is not legal.expression evaluation failed: val is not legal.expression evaluation failed: v("clk_p" ?result "tran")"(\"lowerCase\" 0 t nil (\"*Error* lowerCase: argument #1 should be either a string or a symbol (type template = \\\"S\\\")\" nil))"
But if I write in the ICW :
plot(v("clk_p" ?result "tran"))
It work just fine.
(same if I use getData( ) )
I didn't change anything since for this to happen and I have no idea how to fix it.
In reply to Andrew Beckett:
Sorry for the lack of details.
ICW version : 5.1.41
Simulator : bdasim
Results Browser : Viva 6.1.5
Running from script with PSF output format. If I run interactive simulation from ADE (and setting bdaBrsim simulator) in Cadence 5.1.41, then open the PSF in the results browser of Cadence 6.1.15, I don't have any issue.
It was working just fine last week, my simulation results used to be in psf/tran.tran
Now, it's psf/an1.tran and I can't do anything of it with OCEAN scrip.
In reply to The Setlaz:
And I forgot to mention, when I type :
The command does not return the directory where the results are ? (it's a totally different one - the one from where I started Viva)
The name of the file and its contents are under the control of the simulator. You might want to contact Berkeley Design Automation's customer support, as it's their simulator.