Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I have written a behavioral model using verilog-a and want to simulate it using spectre.
Additionally, I want to study how the statistical variations of some of the parameters defined in my model affect the overal electrical characteristics, that is, I need to do a Monte Carlo simulation for this study.
I know how to do the Monte Carlo simulation provided with foundry PDK, so my problem is whether can I do the Monte Carlo with the parameters that I defined in my verilog-a model and plot the statistical analysis results as a histogram or something?
Thanks if any of you could lend me a hand on this!
There's an example in this solution of how to do this.
In reply to Andrew Beckett:
Thank you for the link to the solution. I've tried it myself and it works. However, I wonder if it's possible to define the statistical parameter with respect to another parameter of the model.
Say I have modeled a current source (see below) and I want the standard deviation to be a certain percentage of the value that the user defines in the schematic for the specific model.
// VerilogA for user, vccs_mc, veriloga
`include "constants.vams"`include "disciplines.vams"
inout vpos,vneg,ipos,ineg;electrical vpos,vneg,ipos,ineg;
(*cds_inherited_parameter*) parameter real gm_mc = 0;
parameter real gm = 1u;localparam real gm_effective = (1+gm_mc)*gm; // nominal transconductance plus monte-carlo mismatch effect
analog beginI(ipos,ineg) <+ gm_effective*V(vpos,vneg);end
How shall I define the variation of the parameter gm_mc in the .scs file such that is taken into account properly ? Currently I have the following:
parameters gm_mc = 0
vary gm_mc dist=gauss std=1 percent=yes
But when I run the Monte Carlo the simulator complains there's no statistical variation.
Thanks in advance.
In reply to Luis Gutierrez:
If I run with your statistics block, I get:
Warning from spectre during Monte Carlo analysis `mc'. WARNING (SFE-3224): Variance of the mismatch parameter `gm_mc' is evaluted to be zero.Error found by spectre during Monte Carlo analysis `mc'. ERROR (SFE-3225): Variance (or standard deviation) of statistical parameters cannot be zero! Set `ignorezerovar=yes' in global options to bypass this check.
This is because you have percent=yes and so the standard deviation is set to be 1% of the mean value (which is 0). That's not going to work.
There's no need to make the standard deviation a function of an instance parameter. What you would do is have a normalized statistical parameter - e.g. a mean of 0, and standard deviation of 1, and then scale it in the model. In this case your model has a standard deviation of gm (if I remove the percent=yes) because you're multiplying gm_mc by gm. If you wanted it to be 1% of gm, you could write:
localparam real gm_effective = (1+gm_mc*0.01)*gm; // nominal transconductance plus monte-carlo mismatch effect
Thanks for the explanation and the workaround Andrew. Your approach indeed does the trick.