Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Can we have a variable with rexMatchp?
My requirement is as below:
a = "m_1"
b = '("m_1" "m_1_1" "m_1_2")
c = setof(i b !rexMatchp("_[1-9]*$" i) // This will return nil.
My desired output for c is "m_1" and at the same time, I want to exclude a_[1-9] where a="m_1"
Could you please guide? Is it possible with rexMatchp?
I'm confused as to what you want, your requirements are mutually exclusive - you want to match "m_1" but you don't want to match a (which is "m_1") - can you clarify your requirement please?
Probably the trick will be to either build the rexMatchp test expression using sprintf() where the variable can be inserted into the test expression [e.g. sprintf(nil "%s*$" a) ], and/or make a more complex condition which can be written as a single compound/composite expression [e.g. "this" || ("that" && "theOther") - this OR (that AND theOther) ].
Anyway, I hope this helps you.
In reply to skillUser:
I assume you want:
rexCompile(strcat(a "_[1-9]*$"))c=setof(i b !rexExecute(i))
This will return ("m_1")
In reply to Andrew Beckett:
Sorry for not being clear. Let me explain what I am trying to do.
"a" could fall under one of the following category.
a = '(m1 m1_1 m1_2...) or a = '(mn_1 mn_1_1 mn_1_2...)
My end goal is to get the "original name (orig_name) with out _[1-9]. And if the original name itself had _[0-9] in it, I need to handle it appropriately.
I have implemented the following to handle this scenario.
if(rexExecute(orig_name) then mainInst = car(setof(i insts !rexMatchp("@" i) && !rexMatchp("_[0-9]_[1-9][0-9]*$" i)))
else parentInst = car(setof(i insts !rexMatchp("@" i) && !rexMatchp("_[1-9][0-9]*$" i)))
Is there a better way to handle this? Thanks.
In reply to adeuser777:
Your requirements are still as clear as mud, I'm afraid. I've really no idea what you are trying to achieve. Originally a was a string - now it is a list. Your example doesn't even mention a so I don't know what you are trying to do.
Best thing is to describe a number of different sets of input and output data - with some detailed description of what you want it to do.
Are you using IC61? If so, the pcre functions allow a lot more power in the regular expressions than the old rex functions.
Isn't this just rexMatchList(strcat(a "$") b) ? Or the car of that if you want the first match?